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Edmond Cheng, 492221 Clover Ridge Dr, Cedar Park, TX 78613

Edmond Cheng Phones & Addresses

2221 Clover Ridge Dr, Cedar Park, TX 78613    512-2500213    512-3353961   

11506 Chancellroy Dr, Austin, TX 78759    512-2500213   

Niagara Falls, NY   

Mentions for Edmond Cheng

Edmond Cheng resumes & CV records

Resumes

Edmond Cheng Photo 30

Test Manager, Mad Derivatives, Mts At Freescale Semiconductor

Position:
Test Manager, MAD Derivatives, MTS at Freescale Semiconductor
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Freescale Semiconductor since May 2012
Test Manager, MAD Derivatives, MTS
Freescale Semiconductor 2008 - Apr 2012
Test Engineering Lead, MTS
Freescale Semiconductor. 2006 - 2008
Senior Test Engineer
Motorola Inc. Jun 1994 - Dec 2005
Product/Test Engineer
Education:
The University of Texas at Austin 1993 - 1997
Bachelor of Science, Electrical Engineering
Edmond Cheng Photo 31

Edmond Cheng

Location:
United States

Publications & IP owners

Us Patents

Method And Apparatus For Testing A Semiconductor Structure Having Top-Side And Bottom-Side Connections

US Patent:
2007009, May 3, 2007
Filed:
Oct 31, 2005
Appl. No.:
11/263089
Inventors:
Edmond Cheng - Cedar Park TX, US
Addi Mistry - Austin TX, US
David Patten - Austin TX, US
International Classification:
G01R 31/26
US Classification:
324765000
Abstract:
A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.

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