Elias H Dagher, 4824647 Royale Rdg, Laguna Beach, CA 92677

7173980, Feb 6, 2007

Sep 20, 2002

10/251663

Wesley K. Masenten - Irvine CA, US
Keith Soo Hoo - Long Beach CA, US
Peter Stubberud - Henderson NV, US
Thang Victor Dinh - Westminster CA, US
Elias Dagher - Aliso Viejo CA, US

DiTrans IP, Inc. - Menlo Park CA

H04L 27/06

375316

An improved complex-IF digital receiver has various improvements. The improved complex-IF digital receiver, for single or dual band applications, preferably synchronizes all of the signals to each other, which may be an integer multiple of each other. For example, the decimation filter, delta-sigma modulator, sensitivity DAC, and other circuits in the receiver can be synchronized. The delta-sigma modulator preferably includes a comparator whose input is coupled to a sensitivity DAC or synchronous dithering circuit. Ideally, the sensitivity DAC forces the comparator to trigger at every clock cycle and reduces the effect of hysteresis and offset at the input of the comparator. The receiver includes a translation circuit that translates an intermediate frequency signal to baseband, where the translation circuit preferably operates a translation ratio that is a multiple of 4.

7692417, Apr 6, 2010

Sep 19, 2005

11/230370

Elias Hani Dagher - Aliso Viejo CA, US

Skyworks Solutions, Inc. - Woburn MA

G05F 1/00

323285, 323288

A voltage converter having a controller capable of maintaining stable operation of a voltage converter over multiple modes of operation. The voltage converter provides a feedback signal to an error signal generator. One or more controllers, which are selectively established as part of the feedback loop, process the error signal to generate a voltage converter charging cycle control signal. A pulse width modulator may be utilized to generate a voltage converter switch control signal that controls the charge cycle. A detector or comparator monitors one or more aspects of operation of the control circuit or the voltage converter to detect changes in the mode of operation. Upon detection of a change, the detector or comparator generate a multi-mode control signal to selectively switch one or more sub-controllers into or out of the feedback loop to thereby maintain desired stability, loop bandwidth, and response time.

8019293, Sep 13, 2011

Mar 7, 2008

12/044203

Elias Dagher - Aliso Viejo CA, US
Kevin Juan - Irvine CA, US
Man H. Ku - Irvine CA, US
Dmitriy Rozenblit - Irvine CA, US

Skyworks Solutions, Inc. - Woburn MA

H01Q 11/12
H04B 1/04

4551271, 455572

A controller enables the integration of a DC-DC converter in an amplitude modulation power control loop in a mobile handset. The controller includes an input conditioner and an event sensor. The input conditioner uses a peak detector to track the output of a regulator and responds to available baseband input signals. The event sensor controls a switch that connects the DC-DC converter to a battery in response to a bypass event. The controller bypasses the DC-DC-converter when a transmitter is not enabled. The DC-DC converter is enabled prior to a transmission burst. A target voltage is determined from a series of detected peak voltages from the output of the regulator. The controller commands the DC-DC converter to transition to the target voltage until the end of a transmission burst.

8639200, Jan 28, 2014

Sep 12, 2011

13/230070

Elias Dagher - Aliso Viejo CA, US
Kevin Juan - Irvine CA, US
Man H. Ku - Irvine CA, US
Dmitriy Rozenblit - Irvine CA, US

Skyworks Solutions, Inc. - Woburn MA

H01Q 11/12
H04B 1/04

4551271, 455572

A controller enables the integration of a DC-DC converter in a mobile handset. The controller includes an input conditioner and an event sensor. The input conditioner uses a peak detector to track the output of a regulator and responds to available baseband input signals. The event sensor directs coupling between a voltage source and the DC-DC converter in response to a bypass event.

2003020, Oct 30, 2003

Apr 29, 2002

10/134300

Elias Dagher - Aliso Viejo CA, US
Matthew Miller - Palatine IL, US

Motorola, Inc.

H03M003/00

341/143000

A sigma-delta analog-to-digital converter () having DEM () facilitated data weighted averaging to select specific unit elements of a negative feedback loop digital-to-analog converter (), which DEM () is comprised substantially of transmission gates that contribute little to propagation delay. As a result, the feedback signal provided by the feedback loop is not more than one clock cycle behind the present coded output of the ADC () itself. As a result, higher resolution converters can be realized. The DEM () utilizes a repeating sequence to select specific unit elements. In some embodiments the direction of sequence usage is reversed in various ways to aid in reducing harmonic distortion.

2022036, Nov 17, 2022

May 13, 2021

17/320077

- San Diego CA, US
Aram Akhavan - San Diego CA, US
Ganesh Kiran - San Diego CA, US
Lei Sun - San Diego CA, US
Elias Dagher - Laguna Niguel CA, US
Dinesh Jagannath Alladi - San Diego CA, US

H03G 3/30
H03M 1/12
H03F 3/19
H03F 3/21

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

2023010, Mar 30, 2023

Sep 24, 2021

17/484581

- San Diego CA, US
Lei Sun - San Diego CA, US
Yuhua Guo - San Diego CA, US
Elias Dagher - Laguna Niguel CA, US
Aram Akhavan - San Diego CA, US
Yan Wang - San Diego CA, US
Dinesh Jagannath Alladi - San Diego CA, US

H03M 1/16
H03M 1/38

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

2023002, Jan 26, 2023

Jul 26, 2021

17/385799

- San Diego CA, US
Seyed Arash Mirhaj - Poway CA, US
Lei Sun - San Diego CA, US
Elias Dagher - Laguna Niguel CA, US

H03M 1/10

An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.