Erik Leigh Hedberg, 682166 Laurel Blossom Cir, Ocoee, FL 34761

6388305, May 14, 2002

Dec 17, 1999

09/466495

Claude L. Bertin - South Burlington VT
Erik L. Hedberg - Essex Junction VT
Russell J. Houghton - Essex Junction VT
Max G. Levy - Essex Junction VT
Rick L. Mohler - Williston VT
William R. Tonti - Essex Junction VT
Wayne M. Trickle - Fairfax VT

International Business Machines Corporation - Armonk NY

H01L 2900

257530, 257520, 257513

A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench.

6396120, May 28, 2002

Mar 17, 2000

09/527191

Claude L Bertin - South Burlington VT
Toshiharu Furukawa - Essex Junction VT
Erik L. Hedberg - Essex Junction VT
Jack A. Mandelman - Stormville NY
William R. Tonti - Essex Junction VT
Richard Q. Williams - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 2972

257530, 257627, 257773

A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.

6420925, Jul 16, 2002

Jan 9, 2001

09/757267

John A. Fifield - Underhill VT
Erik L. Hedberg - Essex Junction VT
Claude L. Bertin - South Burlington VT
Nicholas M. van Heel - Eagle ID

International Business Machines Corporation - Armonk NY

H01H 3776

327525, 327526

According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.

6426530, Jul 30, 2002

May 10, 2000

09/568663

Claude L. Bertin - South Burlington VT
John E. Cronin - Milton VT
Erik L. Hedberg - Essex Junction VT
Jack A. Mandelman - Stormville NY

International Business Machines Corporation - Armonk NY

H01L 2976

257329, 257903

A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO. Each devices gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps.

6426904, Jul 30, 2002

Mar 9, 2001

09/803500

John E. Barth - Williston VT
Claude L. Bertin - South Burlington VT
Jeffrey H. Dreibelbis - Williston VT
Wayne F. Ellis - Jericho VT
Wayne J. Howell - Williston VT
Erik L. Hedberg - Essex Junction VT
Howard L. Kalter - Colchester VT
William R. Tonti - Essex Junction VT
Donald L. Wheater - Hinesburg VT

International Business Machines Corporation - Armonk NY

G11C 2900

365201

Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer.

6567950, May 20, 2003

Apr 30, 1999

09/302917

Claude L. Bertin - South Burlington VT
Timothy J. Dell - Colchester VT
Erik L. Hedberg - Essex Junction VT

International Business Machines Corporation - Armonk NY

G11C 2900

714767

An improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or space chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.

6518112, Feb 11, 2003

Jul 6, 2001

09/899262

Michael D. Armacost - Wallkill NY
Claude L. Bertin - South Burlington VT
Erik L. Hedberg - Essex Junction VT
Jack A. Mandelman - Stormville NY

International Business Machines Corporation - Armonk NY

H01L 31119

438212, 438213

A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the devices channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e. g. , PNPNP or NPNPN, each with its own gate, i. e.

6570254, May 27, 2003

May 31, 2001

09/871087

John B. DeForge - Barre VT
David E. Douse - Hinesburg VT
Steven M. Eustis - Essex Junction VT
Erik L. Hedberg - Essex Junction VT
Susan M. Litten - Jericho VT
Endre P. Thoma - Colchester VT

International Business Machines Corporation - Armonk NY

H01L 2348

257758

Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DTâdeep trench; SSâsurface strap; DIFFâDiffusion; NDIFFâN Diffusion; PDIFFâP Diffusion; WLâN wells; PCâpolysilicon gates; BNâN diffusion Implant; BPâP diffusion Implant; C âfirst contact; M âfirst metal layer; C âsecond contact; and, M2âsecond metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M -C -PC-C -DIFF-C -M -C -M ; M -C -PDIFF-SS-DT-SS-PDIFF-C -M -C -M ; M -C -M -C -PC-C -M ; M -C -M -C -NDIFF-WL-NDIFF-C -M ; and, M -C -M -C -NDIFF-C -M -C -PC-C -M. These conducting paths are electrically opened with the omission of any of the layers in the series path.