Jerry C Cheng, 6061 Twinkle Ct, Milpitas, CA 95035

6380091, Apr 30, 2002

Jan 27, 1999

09/238050

Fei Wang - San Jose CA
Jerry Cheng - Milpitas CA
Darrell M. Erb - Los Altos CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 213065

438706, 438710, 438711, 438712

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first dielectric layer made of an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first dielectric layer, and a second dielectric layer, made of low k dielectric material, is formed on the nitride etch stop layer. A via is etched into the first dielectric layer, and a trench is then etched into the second dielectric layer. The materials if the first and second dielectric layers are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second dielectric layer and not the first dielectric layer.

6472317, Oct 29, 2002

Feb 12, 2001

09/780457

Fei Wang - San Jose CA
Jerry Cheng - Milpitas CA
Simon S. Chan - Saratoga CA
Todd Lukanc - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438638, 438637, 438624, 438738

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

6649525, Nov 18, 2003

Jan 16, 2002

10/050485

Khoi A. Phan - San Jose CA
Jeffrey Erhardt - San Jose CA
Jerry Cheng - Milpitas CA
Richard J. Bartlett - Bonny Doon CA
Anthony P. Coniglio - San Jose CA
Wolfram Grundke - Dresden, DE
Carol M. Bradway - Austin TX
Daniel E. Sutton - Austin TX
Martin Mazur - Pulsnitz, DE

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21461

438694, 438689, 438690, 438715, 438724, 438725

Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

6756300, Jun 29, 2004

Dec 18, 2002

10/324259

Fei Wang - San Jose CA
Jerry Cheng - Milpitas CA
Lynne A. Okada - Sunnyvale CA
Minh Quoc Tran - Milpitas CA
Lu You - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438637

For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

2013027, Oct 17, 2013

Apr 13, 2012

13/446679

Jerry Cheng - Mountain View CA, US
Erik Jessen - Belmont CA, US
Eric Hennings - San Jose CA, US

YAHOO! INC. - Sunnyvale CA

G06F 17/30

707769, 707E17014

Method, system, and programs for content search are disclosed. A user interface configured based on context information is presented within a host application. A plurality of selectable search results are then fetched based on the context information and a query received from a user through the user interface. An input associated with a selection of one or more selectable search results is received from the user through the user interface. The user interface is updated based on the plurality of selectable search results. In response to the selection, the one or more selected search results are provided to the host application with the context information.

2013028, Oct 24, 2013

Apr 24, 2012

13/454185

Ethan Batraski - Foster City CA, US
Olivia Franklin - San Francisco CA, US
Jerry Cheng - Mountain View CA, US
Scott Fish - San Carlos CA, US

YAHOO! INC. - Sunnyvale CA

G06F 3/048

715783

Method, system, and programs for displaying search results are disclosed. A first page that contains a first piece of content is presented to a user. A second page that contains a second piece of content including one or more search results is generated. The second page is arranged behind the first page such that the second page is invisible to the user. A first triggering event associated with a predetermined user input is detected. In response to the first triggering event, at least part of the first page is moved in a direction from a default position for a distance to expose at least part of the second page such that the second piece of content on the second page becomes visible to the user.

6207577, Mar 27, 2001

Jan 27, 1999

9/238049

Fei Wang - San Jose CA
Jerry Cheng - San Jose CA
Darrell M. Erb - Los Altos CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L21/3065

438706

A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.

6291887, Sep 18, 2001

Jan 4, 1999

9/225220

Fei Wang - San Jose CA
Jerry Cheng - Milpitas CA
Todd Lukanc - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2348

257758

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.