Jianhua L Liu, 61136 Blue Spruce Ln, Union City, CA 94587

8176111, May 8, 2012

Jan 14, 2008

12/008785

Jianhua Liu - San Jose CA, US
Gregg William Baeckler - San Jose CA, US

Altera Corporation - San Jose CA

G06F 7/487

708504, 708654

An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion of the bits of the pre-scaled fractional divisor. This value is used to scale the fractional operands and a multiply-add operation is used based on principles of series expansion to compute a final result with an acceptable degree of accuracy.

2021009, Apr 1, 2021

Sep 27, 2019

16/586891

Jianhua Liu - San Jose CA, US
Chienkuang Chen - Santa Clara CA, US

GOWIN Semiconductor Corporation - GangZhou

H03K 19/177

A programmable logic device (“PLD”) contains programmable digital signal processing (“DSP”) blocks operable to be selectively programmed to perform one or more logic functions. The PLD, in one embodiment, includes configurable logic blocks (“LBs”), an input and output (“I/O”) block, and programmable DSP blocks. The configurable LBs are able to be selectively programmed to perform one or more logic functions. The I/O block includes I/O ports for facilitating data transfer. The programmable DSP blocks are configured to perform various predefined logic functions. Each of the programmable DSP blocks, in one aspect, includes at least one configurable DSP which, in one embodiment, includes a 27×18 multiplier and a 12×12 multiplier.

2020017, Jun 4, 2020

Jan 13, 2020

16/741393

- GuangZhou, CN
Jianhua Liu - Fremont CA, US
Ning Song - Cupertino CA, US

GOWN Semiconductor Corporation - GuangZhou

H03K 19/17784
H03K 19/17724
H03K 19/17772

A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

2020014, May 7, 2020

Dec 30, 2019

16/730716

Jinghui Zhu - San Jose CA, US
Jianhua Liu - Fremont CA, US
Ning Song - Cupertino CA, US

GOWN Semiconductor Corporation - GuangZhou

H03K 19/17784
H03K 19/17724

A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.