Jin H LeeMorgan Hill, CA

6509622, Jan 21, 2003

Aug 23, 2000

09/644639

Qing Ma - San Jose CA
Jin Lee - Palo Alto CA
Quan Tran - San Jose CA
Harry Fujimoto - Sunnyvale CA

Intel Corporation - Santa Clara CA

H01L 27095

257483, 438132, 438215, 438601

An integrated circuit including a die having a circuit area and a plurality of guard rings. The circuit area includes active devices, passive devices, and interconnects connected to form an integrated circuit. The plurality of guard rings includes a plurality of stacked guard rings having substantially equal widths and encircling the circuit area. Alternatively, the plurality of guard rings includes metallization level guard rings interleaved with one or more via level guard rings. Each of the one or more via level guard rings includes one or more guard rings encircling the circuit area. Alternatively, the plurality of guard rings includes a plurality of concentric guard rings encircling the circuit area. Each of the plurality of guard rings is fabricated from a metal, such as aluminum, copper, or silver, or an alloy of aluminum, copper, or silver.

6537706, Mar 25, 2003

Mar 14, 2000

09/525198

Qing Ma - San Jose CA
Jin Lee - Palo Alto CA
Jun Fei Zheng - Mountain View CA
Giang Dao - Fremont CA

Intel Corporation - Santa Clara CA

G03F 900

430 5, 430323, 430296, 430394, 378 35

A method for making a photolithographic mask. The method comprises forming a film on a substrate that deforms the substrate, and applying a deformation reducing agent to the substrate to reduce the amount of deformation that the film caused. In a preferred embodiment, the deformation reducing agent comprises one or more films, which are formed on one side of the substrate, that balance the substrate deformation effect of one or more films that are deposited on the other side of the substrate. The film or films that constitute the deformation reducing agent may be similar to, or different from, an absorption film and/or any other films deposited on the substrate or on the absorption film.

6737754, May 18, 2004

Feb 5, 2001

09/777833

Qing Ma - San Jose CA
Jin Lee - Palo Alto CA
Chun Mu - Saratoga CA
Quat Vu - Santa Clara CA
Jian Li - Sunnyvale CA
Larry Mosley - Sunnyvale CA

Intel Corporation - Santa Clara CA

H01L 2328

257796, 257707, 257712, 257713

A semiconductor device having a multilayer laminate that includes a thermally stable, flexible polymer film, a semiconductor die, a molding compound, and a heat dissipation member. The die has an active surface and an inactive surface, in which the active surface includes a plurality of contacts. The molding compound contacts both the laminate and the die, but does not contact the dies active or inactive surfaces. The heat dissipation member contacts the dies inactive surface.

6876053, Apr 5, 2005

Aug 13, 1999

09/374502

Qing Ma - San Jose CA, US
Jin Lee - Mountain View CA, US
Harry Fujimoto - Sunnyvale CA, US
Changhong Dai - San Jose CA, US
Travis Eiles - San Jose CA, US
Krishna Seshan - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L029/00
H01L029/76
H01L031/113
H01L031/119

257500, 257369, 257374, 257499, 257401, 257506

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i. e. , to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

7410858, Aug 12, 2008

May 19, 2006

11/437379

Qing Ma - San Jose CA, US
Jin Lee - Mountain View CA, US
Harry Fujimoto - Sunnyvale CA, US
Changhong Dai - San Jose CA, US
Travis Eiles - San Jose CA, US
Krishna Seshan - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L 29/72

438221, 438197, 438404, 438424, 438694

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i. e. , to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

7411269, Aug 12, 2008

Mar 28, 2005

11/091967

Qing Ma - San Jose CA, US
Jin Lee - Mountain View CA, US
Harry Fujimoto - Sunnyvale CA, US
Changhong Dai - San Jose CA, US
Travis Eiles - San Jose CA, US
Krishna Seshan - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L 29/72

257510, 257401, 257506, 257622

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i. e. , to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

2007001, Jan 18, 2007

Sep 22, 2006

11/525982

Qing Ma - San Jose CA, US
Jin Lee - Mountain View CA, US
Harry Fujimoto - Sunnyvale CA, US
Changhong Dai - San Jose CA, US
Travis Eiles - San Jose CA, US
Krishna Seshan - San Jose CA, US

H01L 29/00

257506000

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

2008021, Sep 4, 2008

Oct 16, 2007

11/975008

Jin Hyung Lee - Mountain View CA, US
Won-Seok Seo - Seoul, KR
Hongjie Dai - Cupertino CA, US
Zhuang Liu - Stanford CA, US
Sarah Paige Sherlock - New Haven VT, US

A61K 49/06
B32B 5/16
C12N 5/06
A61P 35/00
A61K 33/00
C12N 13/00

424 932, 428403, 435325, 4351731, 424600

Disclosed are nanocrystals comprising metals and metal alloys, which are formed by a process that results in a layer of graphite in direct contact with the metallic core. The nanocrystals may be used in vivo as MRI contrast agents, X-ray contrast agents, near IR (NIR) heating agents, drug delivery, protein separation, catalysis etc. The nanocrystals may be further functionalized with a hydrophilic coating, e.g., phospholipid-polyethylene glycol, which improves in vivo stability. The process comprises chemical vapor deposition of metals adsorbed onto silica as a fine powder, in conjunction with a carbon containing gas, which coats the metal particles. The silica is then etched away. Preferred metals include iron, gold, cobalt, platinum, ruthenium and mixtures thereof, e.g., FeCo and AuFe. The process permits control of the alloy compositions, size, and other characteristics.