Jitendra R Kulkarni, 567017 Hollow Lake Way, San Jose, CA 95120

2008005, Feb 28, 2008

Nov 9, 2006

11/558061

Pranav Ashar - Belle Mead NJ, US
Jitendra Kulkarni - San Jose CA, US
Ashwini Choudhary - San Jose CA, US

NetFortis, Inc. - Mountain View CA

G06F 17/50

716 2, 716 4

An efficient finite state machine implementation of a string matching that relies upon a Content Addressable Memory (CAM) or a CAM-equivalent collision-free hash-based lookup architecture with zero false positives used as a method for implementing large FSMs in hardware using a collision-free hash-based look up scheme with low average case bandwidth and power requirements that overcomes prior art limitations by providing the ability to match an anchored or unanchored input stream against a large dictionary of long and arbitrary length strings at line speed. It should be noted that in the context of the described embodiments, a string could take many forms, such as a set of characters, bits, numbers or any combination thereof.

2008006, Mar 13, 2008

Oct 17, 2006

11/550320

Ashwini Choudhary - San Jose CA, US
Pranav Ashar - Belle Mead NJ, US
Jitendra Kulkarni - San Jose CA, US

NetFortis, Inc. - MountainView CA

G06F 7/00

707 7

String matching a first string to a string stored in a string dictionary is performed by k-way hashing the first string and locating corresponding k hash locations in a first memory. When any of the k hash locations has a zero Bloom bit, the first string is deemed to not match any of the strings in the string dictionary. Otherwise, a sub-set of the k hash locations identified as those k hash locations having non-zero Bloom bits and a unique bit set to 1 each include a pointer that points to a string in the string dictionary that is fetched and compared to the first string wherein the fetches from the string dictionary are interleaved over the addresses from the first memory. A match signal is issued when the first string matches at least one of the strings stored in the dictionary.

5365479, Nov 15, 1994

Mar 3, 1994

8/206446

Loc B. Hoang - San Jose CA
Khoi V. Dinh - San Jose CA
Jitendra R. Kulkarni - Mountain View CA

National Semiconductor Corp. - Santa Clara CA

G11C 1140

36518929

A novel row decoder/driver circuit in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions containing the pull-up and pull-down transistors are biased by voltages which are switched during erasure depending on whether the row line is selected or deselected in order to assure that excessive voltages do not appear across based upon the voltage levels applied to the transistors.

2016002, Jan 28, 2016

Jun 25, 2015

14/750555

- San Jose CA, US
Sanjeev Dwarakanath - Bangalore, IN
Jitendra Ramkrishna Kulkarni - San Jose CA, US
Rishi Agarwal - Santa Clara CA, US

H02J 7/00

Techniques for controlling the charging of portable devices are described herein. In an example embodiment, an apparatus comprises a controller coupled to a Universal Serial Bus (USB) port that is configured as a dedicated charging port (DCP). The controller is configured to detect whether a battery-charging (BC) compliant device or a BC non-compliant device is attached to the USB port. When a BC compliant device is detected, the controller controls the charging of the BC compliant device (e.g., by providing a maximum of 1.5 A of charging current). When a BC non-compliant device is detected, the controller controls the charging of the BC non-compliant device by providing a higher (e.g., up to 2.4 A) charging current.

2015005, Feb 19, 2015

May 23, 2014

14/286183

- Suwon-si, KR
Jitendra Kulkarni - San Jose CA, US
Chenjie Luo - Santa Clara CA, US
Simon Bloch - Mountain View CA, US

Samsung Electronics Co., Ltd. - Suwon-si

G06F 1/32
G06F 9/44

713300, 713320

A computing system includes: a storage interface configured to access an application code including a target code; a control unit, coupled to the storage interface, configured to: identify a consumption model corresponding to the target code, calculate a consumption estimate for the target code based on the consumption model, and generate a code-power analysis output based on the consumption estimate.