John A Schadt Deceased330 Gallery Ln, Mount Bethel, PA 18343

6404226, Jun 11, 2002

Sep 21, 1999

09/400029

John Anthony Schadt - Bethlehem PA

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19177

326 41, 326 39, 326101, 326 47, 257209, 257203, 257210, 257211

An integrated circuit comprises an array of standard cell logic having spare gate logic dispersed therein. The spare gate logic is connectable to the standard cell logic through upper level conductors. This allows the design of an integrated circuit to be changed by changing the pattern of the upper level conductors, thereby lowering the cost of making a design change and reducing the disturbance of the original wiring. In an illustrative embodiment, the top two or three metal levels and associated vias are mask-programmable for this purpose. The interconnections from the mask-programmable upper levels to the underlying standard cell logic is accomplished using a regular array of conductor vias interspersed throughout the standard cell array, plus elevated output terminal which create a loop structure completed by the program levels. This allows output terminal loops of the standard cells to be brought up to the mask-programmable metal levels for removal of any standard cell logic. The spare gate logic comprises a relatively small percentage of logic gates as compared to the standard cell logic (typically less than 20 percent).

6600341, Jul 29, 2003

Apr 30, 2002

10/135325

Craig Bingert - Allentown PA
Christopher D. Gorsuch - Walnutport PA
Oscar G. Mercado - Bethlehem PA
Anthony K. Myers - Hamburg PA
John A. Schadt - Bethlehem PA
Brian W. Yeager - Schuykill Haven PA

Lattice Semiconductor Corp. - Hillsboro OR

H03K 1900

326102, 326 38, 326 44, 257202

An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern.

6814296, Nov 9, 2004

Apr 30, 2002

10/135308

Jay H. Angle - Whitehall PA
Christopher D. Gorsuch - Walnutport PA
Oscar G. Mercado - Bethlehem PA
Anthony K. Myers - Hamburg PA
John A. Schadt - Bethlehem PA
Brian W. Yeager - Schuykill Haven PA

Lattice Semiconductor Corp. - Hillsboro OR

G06K 1906

235492, 705 7

Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool.

6822477, Nov 23, 2004

Jun 20, 2003

10/600042

Craig Bingert - Allentown PA
Christopher D. Gorsuch - Walnutport PA
Oscar G. Mercado - Bethlehem PA
Anthony K. Myers - Hamburg PA
John A. Schadt - Bethlehem PA
Brian W. Yeager - Schuykill Haven PA

Lattice Semiconductor Corp. - Hillsboro OR

H03K 19117

326 41, 341 38, 341 44

An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.

6870395, Mar 22, 2005

Mar 18, 2003

10/391094

John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H01L025/00
H03K019/177
H03K017/693
G06F017/50

326 41, 716 14, 716 16

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

6877667, Apr 12, 2005

Aug 13, 2003

10/640804

Jay H. Angle - Whitehall PA, US
Christopher D. Gorsuch - Walnutport PA, US
Oscar G. Mercado - Bethlehem PA, US
Anthony K. Myers - Hamburg PA, US
John A. Schadt - Bethlehem PA, US
Brian W. Yeager - Schuykill Haven PA, US

Lattice Semiconductor Corporation - Hillsboro OR

G06K019/06

235492, 235375

Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool.

6940779, Sep 6, 2005

Aug 13, 2003

10/641260

Zheng (Jeff) Chen - Macungie CA, US
John Schadt - Bethlehem PA, US
Barry Britton - Orefield PA, US

Lattice Semiconductor Corporation - Hillsboro OR

G11C007/00

36523003, 36523001, 36523005, 36518908, 326 38, 326 41

Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.

6975137, Dec 13, 2005

Feb 10, 2005

11/055280

John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US

Lattice Semiconductor Corporation - Hillsboro OR

G06F007/38
G06F017/50
H03K019/177
H03K019/00

326 39, 716 16

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.