Jonathon Carl Skarphol, 46300 W Main St, Robins, IA 52328

2008030, Dec 11, 2008

Jun 6, 2007

11/758851

Duane Arlyn Averill - Rochester MN, US
Jonathon C. Skarphol - Cedar Rapids IA, US
Brian T. Vanderpool - Byron MN, US

G06F 12/08

711146, 711E12057

A data processing system includes a coherence directory having a prefetch sector cache and a memory directory array containing a plurality of sectored entries. According to one method, in response to receiving a first directory lookup request specifying a first target address, an entry associated with the target address is accessed in the memory directory array. In response to the access, the coherence directory returns, as a result of the first directory lookup request, contents of a first sector that is identified by the target address as a requested sector. The coherence directory also caches contents of a second sector of the multiple sectors that is a non-requested sector for the first directory lookup request in a prefetch sector cache. In response to receiving a subsequent second directory lookup request specifying a second target address that identifies the second sector as a requested sector, the coherence directory accesses the contents of the second sector in the sector prefetch cache and returns the contents of the second sector as a result of the second directory lookup request.

2022038, Dec 1, 2022

May 26, 2021

17/331237

- Cedar Rapids IA, US
Sean Nichols - Marion IA, US
Jonathon C. Skarphol - Robins IA, US
Sean Jarrard - Cedar Rapids IA, US
Brian R. Roggendorf - Marion IA, US
Ronald Luse - Marion IA, US
James A. Marek - Anamosa IA, US

G06F 9/38
G06F 9/54
G06N 5/02

A cross-domain guard is disclosed that includes a field programmable gate array (FPGA). The FPGA includes a rule database containing one or more rules, a memory interconnect configured to send control data or rule processing data, media access control logic, and a plurality of filter engines configured to receive an incoming message and generate a processed message. Each of the plurality of filter engines may contain a message processing allocation element configured to receive and distribute the incoming message, and a plurality of rule processor kernels. Each of the plurality of rule processor kernels includes a rule processor kernel control element, a plurality of data operator kernels configured to perform a data comparison operation, a ternary lookup table processor configured to perform a logic operation based upon a result of the data comparison operation, and a processed message arbiter. A method for filtering incoming messages is also disclosed.