Jyshyang S Chen, 641454 Poppy Way, Cupertino, CA 95014
Jyshyang Chen Phones & Addresses
1454 Poppy Way, Cupertino, CA 95014 408-6461899
San Jose, CA
San Francisco, CA
Fremont, CA
Arlington, TX
Santa Clara, CA
Mentions for Jyshyang S Chen
Publications & IP owners
Us Patents
Vpn And Firewall Integrated System
US Patent:
7596806, Sep 29, 2009
Filed:
Sep 8, 2003
Appl. No.:
10/658561
Inventors:
Jyshyang Chen - Cupertino CA, US
Assignee:
O2Micro International Limited - Georgetown, Grand Cayman
International Classification:
G06F 15/16
US Classification:
726 11, 726 12, 726 13, 713153
Abstract:
The present invention provides an integrated VPN/firewall system that uses bath hardware (firmware) and software to optimize the efficiency of both VPN and firewall functions. The hardware portions of the VPN and firewall are designed in flexible and scalable layers to permit high-speed processing without sacrificing system security. The software portions are adapted to provide interfacing with hardware components, report and rules management control.
Robust And Economic Solution For Fpga Bit File Upgrade
US Patent:
7772882, Aug 10, 2010
Filed:
Jun 23, 2008
Appl. No.:
12/144493
Inventors:
Licai Fang - Haidian District, CN
Lin Gan - Haidian District, CN
Shunguang Ding - Tongzhou District, CN
Jyshyang Chen - Cupertino CA, US
Lin Gan - Haidian District, CN
Shunguang Ding - Tongzhou District, CN
Jyshyang Chen - Cupertino CA, US
Assignee:
O2Micro International Limited - Grand Cayman
International Classification:
H03K 19/173
G06F 11/20
G06F 11/14
G06F 11/20
G06F 11/14
US Classification:
326 46, 326 37, 711162, 714 6, 714 54
Abstract:
A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.
Network Interface System With Filtering Function
US Patent:
7852756, Dec 14, 2010
Filed:
Jun 13, 2007
Appl. No.:
11/818307
Inventors:
Jyshyang Chen - Cupertino CA, US
Chao Jiang - Beijing, CN
Chao Jiang - Beijing, CN
Assignee:
02Micro International Limited - Grand Caymna
International Classification:
H04L 12/22
H04L 12/26
H04L 12/26
US Classification:
370229, 370235, 370412
Abstract:
A network interface system with packet filtering function is disclosed herein. The network interface system includes interfaces, a packet buffer and a controller. The packet buffer stores data packets received by the network interface system. The controller provides security defense for the host system and the network by filtering the data packets stored in the packet buffer. The controller controls the packet buffer abandoning a data packet if the data packet is identified as an unsafe packet. The controller also includes a regulator for controlling a transferring order of the data packets. Thus, the network interface system can drop unsafe data packet and transfer data packets considered as safe information. The data packets can be processed in a sequence according to preset priority rules.
Network Interface System With Filtering Function
US Patent:
8165020, Apr 24, 2012
Filed:
Dec 6, 2010
Appl. No.:
12/961258
Inventors:
Jyshyang Chen - Cupertino CA, US
Chao Jiang - Beijing, CN
Chao Jiang - Beijing, CN
Assignee:
O2Micro International Limited - Grand Cayman
International Classification:
H04L 12/22
H04L 12/56
H04L 12/56
US Classification:
370229, 370235, 370412
Abstract:
A network interface system for transferring a data packet between a host system and a network includes multiple matchers and multiple queues. The matchers match the data packet with multiple rules from the host system to generate multiple matching results and allocate a transferring priority to the data packet according to the rules. The queues correspond to the matchers respectively. A queue of the queues stores information indicating the transferring priority for the data packet according to the matching results and priorities of matchers.
Anti-Virus And Firewall System
US Patent:
8316439, Nov 20, 2012
Filed:
May 17, 2007
Appl. No.:
11/804494
Inventors:
Licai Fang - Beijing, CN
Jyshyang Chen - Cupertino CA, US
Donghui Yang - Beijing, CN
Jyshyang Chen - Cupertino CA, US
Donghui Yang - Beijing, CN
Assignee:
Iyuko Services L.L.C. - Dover DE
International Classification:
H04L 29/06
US Classification:
726 22, 726 2, 726 3, 726 12, 726 23, 726 24, 713192, 713189, 713153, 709238, 709230, 709227, 710268, 710267, 710266, 710100
Abstract:
An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.
Robust And Economic Solution For Fpga Bitfile Upgrade
US Patent:
2006024, Nov 2, 2006
Filed:
Aug 18, 2005
Appl. No.:
11/207355
Inventors:
Licai Fang - Beijing, CN
Lin Gan - Beijing, CN
Shunguang Ding - Beijing, CN
Jyshyang Chen - Cupertino CA, US
Lin Gan - Beijing, CN
Shunguang Ding - Beijing, CN
Jyshyang Chen - Cupertino CA, US
International Classification:
H03K 19/173
US Classification:
326038000
Abstract:
A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.
Vpn And Firewall Integrated System
US Patent:
2010013, Jun 3, 2010
Filed:
Sep 29, 2009
Appl. No.:
12/569147
Inventors:
Jyshyang Chen - Cupertino CA, US
Assignee:
O2MICRO, INC. - Santa Clara CA
International Classification:
G06F 15/16
US Classification:
726 11, 713153, 726 12, 726 13
Abstract:
The present disclosure provides an integrated VPN/Firewall system that uses both hardware (firmware) and software to optimize the efficiency of both VPN and firewall functions. The hardware portions of the VPN and firewall are designed in flexible and scalable layers to permit high-speed processing without sacrificing system security. The software portions are configured to provide interfacing with hardware components, report and rules management control.
System With Session Synchronization
US Patent:
2010021, Aug 19, 2010
Filed:
Feb 11, 2010
Appl. No.:
12/703987
Inventors:
JyShyang CHEN - Cupertino CA, US
Hui YANG - Wuhan, CN
Yu ZHAO - Wuhan, CN
Hui YANG - Wuhan, CN
Yu ZHAO - Wuhan, CN
International Classification:
G06F 17/30
G06F 15/16
G06F 15/16
US Classification:
707622, 709228, 709248, 707E17044, 707E17005, 707E17032
Abstract:
A computer-readable medium having computer-executable modules is disclosed. The computer-executable modules include a first session database for storing multiple sessions indicating information interchange between at least two communicating devices. The computer-executable modules further include a controller operable for selecting a session from the first session database according to a session update rate indicating the number of sessions updated in the first session database during a given period of time and for synchronizing the session from the first session database to a second session database.
Possible Relatives
NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.