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K S Venkatraman7219 Langwood St, Beaverton, OR 97123

K Venkatraman Phones & Addresses

7219 Langwood St, Hillsboro, OR 97123    503-2599844   

Issaquah, WA   

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K S Venkatraman

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Work

Company: Nvidia corporation Sep 2006 Position: Senior architect

Education

Degree: MS School / High School: Villanova University 1995 to 1997 Specialities: Electrical Engineering

Interests

Linux system administration, Amateur Radio

Industries

Computer Hardware
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Mentions for K S Venkatraman

K Venkatraman resumes & CV records

Resumes

K Venkatraman Photo 18

K S Venkatraman

Position:
Senior Architect at Nvidia Corporation
Location:
Portland, Oregon Area
Industry:
Computer Hardware
Work:
Nvidia Corporation since Sep 2006
Senior Architect Stexar Corporation Feb 2005 - Aug 2006
Senior Architect Intel Corporation Jul 1997 - Feb 2005
Microprocessor Architect
Education:
Villanova University 1995 - 1997
MS, Electrical Engineering Birla Institute of Technology 1990 - 1994
BE, Electronics and Comunication Patna Science College 1988 - 1990
Intermediate Science, Physics, Chemistry, Mathematics St. Michael's High School 1980 - 1988
Interests:
Linux system administration, Amateur Radio

Publications & IP owners

Us Patents

Method And Apparatus For Prefetching Data To A Lower Level Cache Memory

US Patent:
7383418, Jun 3, 2008
Filed:
Sep 1, 2004
Appl. No.:
10/933188
Inventors:
Kenneth J. Janik - Beaverton OR, US
K S Venkatraman - Hillsboro OR, US
Anwar Rohillah - Hillsboro OR, US
Eric Sprangle - Portland OR, US
Ronak Singhal - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 9/34
G06F 9/26
US Classification:
711216, 711137, 711117, 711118, 711119, 710 52
Abstract:
A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.

Page Handling Efficiency In A Multithreaded Processor

US Patent:
2005003, Feb 10, 2005
Filed:
Sep 13, 2004
Appl. No.:
10/940894
Inventors:
K Venkatraman - Hillsboro OR, US
International Classification:
G06F012/08
US Classification:
711118000, 711207000
Abstract:
In a multithreaded processor, the efficiency of instruction processing may be improved by suspending an executing thread during the translation of a virtual memory address to a physical memory address when the address translation data must be retrieved from storage external to the processor. The suspension of an executing thread allows an address translation to be performed for an instruction in another thread while the address translation data needed for the first thread is retrieved.

Possible Relatives

Kannan S Venkatraman  Meera P Venkatraman  Ramesh Venkatraman  Subramanian Venkatraman  Suresh Venkatraman  Uma Venkatraman  Bharathi A Venkatraman  K R Johnson  K Jones  K C Mcintosh 

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