Tzu Ching Chen, 5814441 Sanford Ave, Flushing, NY 11355

4994773, Feb 19, 1991

Oct 13, 1988

7/257482

Tzu H. Chen - East Brunswick NJ
Mahesh Kumar - Lawrenceville NJ

H03H 1120

333164

A digitally controlled active phase shifter with vernier control consists of a 180 degree phase bit in series with a 90 degree bit and a digitally controlled active vector generator with vernier control. The digitally controlled active vector generator consists of an active power divider with digitally adjustable amplitude, a pair of phase delay networks with an active power combiner employing vernier control. The power divider consists of two sets of parallel pairs of FET's in cascode configuration with all input nodes connected together and all output nodes from the same set tied together. The FET at the output node of each pair is a common gate configuration with its gate RF grounded through a bypass capacitor. The gate bias voltage is applied to the common gate FET to switch it ON or OFF to thereby provide a set of desired signal amplitudes which can be obtained by selecting the gain of each of the cascode stages in each of the parallel pairs. Two output signals from the power divider are fed into a pair of phase delay networks to get 90 degree phase differences.

5150083, Sep 22, 1992

Aug 9, 1990

7/565877

Tzu H. Chen - East Brunswick NJ
Mahesh Kumar - Lawrenceville NJ

Siemens Aktiengesellschaft - Berlin and Munich

H04Q 100

333103

There is described a 2. times. 2 switch matrix which includes four 1. times. 1 switch matrix modules. Each 1. times. 1 switch matrix module consists of an active power divider switch (APDS), an active power combiner switch (APCS) and an air bridge crossover. Additional APDSs and APCSs are utilized in the matrix to compensate for path length differences between different input to output signal paths thus providing good phase and amplitude tracking. The basic switch matrix modules are utilized to form a 2. times. 2 switch matrix whereby two primary input ports can be connected to any one of two primary output ports. The 2. times. 2 switch matrix is utilized to formulate larger matrix arrays as N. times. M configuration. Each of the active power divider switches and power combiner switches utilize two separate dual gate FETs which are suitably interconnected, depending upon whether the circuit is to be used as a power combiner or power divider.