Maged M Michael, 583 Maplewood Dr, Danbury, CT 06811

6338123, Jan 8, 2002

Mar 31, 1999

09/281787

Douglas J. Joseph - Danbury CT
Maged M. Michael - Danbury CT
Ashwini Nanda - Mohegan Lake NY

International Business Machines Corporation - Armonk NY

G06F 1200

711144, 711130, 711156

A method and structure for a system for maintaining coherence of cache lines in a shared memory multiplexor system comprises a system area network and a plurality of compute nodes connected to the system area network. Each of the computer nodes includes a local main memory, a local shared cache and a local coherence controller and computer nodes external to a given compute node include external shared caches and the coherence controller includes shadow directories, each corresponding to one of the external shared caches. Each of the shadow directories includes state information of the local main memory cached in the external shared caches. The shadow directories include only state information of the local main memory cached in the external shared caches.

6405292, Jun 11, 2002

Jan 4, 2000

09/477537

Douglas J. Joseph - Danbury CT
Maged M. Michael - Danbury CT
Ashwini Nanda - Mohegan Lake NY

International Business Machines Corp. - Armonk NY

G06F 1200

711150, 711156, 711168, 711149, 711131

For a cache-coherent controller for a multiprocessor system sharing a cache memory, a split pending buffer having two components: a fully-associative part and an indexed part that can easily be made multi-ported. The associative part, PBA, include multiple entries having a valid bit and address fields, and the indexed part, PBC, includes entries including all the other status fields (i. e. , the content part of the pending buffer entries). The split multi-ported pending buffer enables one request and one or more responses to be handled concurrently. Handling a request requires an associative lookup of PBA, a possible directory lookup, a possible read of PBC (in case of collision), and after processing the request in a request protocol handling unit, a possible PBA update, a possible PBC update, and a possible directory update, depending upon the cache coherence protocol implemented. Handling a response requires no PBA lookup, no directory lookup, a PBC read, and after processing the response in a response protocol handling unit, a possible PBA update, a possible PBC update, and a possible directory update, depending upon the cache coherence protocol implemented.

6628615, Sep 30, 2003

Jan 18, 2000

09/484745

Douglas J. Joseph - Danbury CT
Maged M. Michael - Danbury CT
Ashwini Nanda - Mohegan Lake NY

International Business Machines Corporation - Armonk NY

G06F 1516

370231, 370252, 370409, 709230, 709238

A system and method for communicating messages between nodes of a packet switched communications network, with each message having a defined message type and including message content. The system includes one or more second level channel interface devices connected with a first node for tracking information relating to bi-directional communication of packets over a communications channel established between the first and second network nodes; a device for receiving packets associated with messages from the first node and generating message flits associated with the messages for communication over the channel based on message content associated with the received message packets; a device for receiving message flits associated with messages communicated from a second node and received via the channel and generating corresponding message packet content for storage at the first node; and, one or more first level channel interface devices associated with one or more second level channel interface devices and interfaced to a network switch device at each first and second node for communicating flits to and from a respective first and second node via the channel, wherein the communications channel established between the first and second network nodes includes a first and second level channel selected according to the message content.

6721858, Apr 13, 2004

Aug 24, 2000

09/644988

Douglas J. Joseph - Danbury CT
Maged M. Michael - Danbury CT
Ashwini Nanda - Mohegan Lake NY

International Business Machines Corporation - Armonk NY

G06F 1200

711153, 711173, 711157, 712 13

A method and system for the parallel implementation of protocol engines based on memory partitioning. The method comprises the steps of partitioning a shared memory space into multiple mon-overlapping regions; and for each of the regions, using a respective one protocol engine to handle references to the region, independently of the other protocol engines. Preferably, the memory is partitioned into the non-overlapping regions either by using address interleaving or by using address range registers to identify address ranges for said regions. Also, preferably the protocol engines operate independent of each other and handle accesses to the memory regions in parallel.

6826651, Nov 30, 2004

Mar 7, 2001

09/801036

Maged M. Michael - Danbury CT
Ashwini Nanda - Mohegan Lake NY

International Business Machines Corporation - Armonk NY

G06F 1208

711119, 711133, 711144, 711145

A system and method of maintaining consistent cached copies of memory in a multiprocessor system having a main memory, includes a memory directory having entries mapping the main memory, an access history information in the memory directory entries, and a directory cache having records corresponding to a subset of the memory directory entries. The memory directory may be a full map directory having entries mapping all of the main memory or a sparse directory having entries mapping to a subset of the main memory. The method includes the steps of receiving a signal indicating a processor cache miss, retrieving a memory directory entry from the memory directory, updating the access history of the memory directory entry, selecting a directory cache line based on its access history and allocating the directory cache line for replacement, and writing the memory directory entry into the directory cache.

6996665, Feb 7, 2006

Dec 30, 2002

10/334427

Donald R. DeSota - Portland OR, US
Bruce M. Gilbert - Beaverton OR, US
Robert Joersz - Portland OR, US
Eric N. Lais - Tillson NY, US
Maged M. Michael - Danbury CT, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711109, 711108, 711140, 711169, 712216, 712217, 712218, 712219

A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.

7210018, Apr 24, 2007

Dec 30, 2002

10/334855

Donald R. DeSota - Portland OR, US
Bruce M. Gilbert - Beaverton OR, US
Robert Joersz - Portland OR, US
Thomas D. Lovett - Portland OR, US
Maged M. Michael - Danbury CT, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711169

A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.

7290085, Oct 30, 2007

Nov 16, 2004

10/989751

Maged M. Michael - Danbury CT, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711108, 711141, 711156, 711221, 365 49

A method for accessing a protocol table includes providing a content addressable protocol table comprising a plurality of entries, wherein each entry includes a key field and an output field, constructing a key value from a protocol input, associatively searching the table for an entry whose key field matches the key value constructed from the input, and returning the output field of an entry whose key field matches that of the key value. The table optionally includes a mask field, and searching the table includes seeking the entry whose key field matches a bitwise AND of its mask field with the key value. An error is generated if no matching entry is found on the table.