Makarand Ramkrishna Kulkarni, 573009 Greenhill Dr, Plano, TX 75093

7855090, Dec 21, 2010

Aug 4, 2010

12/850415

Makarand R. Kulkarni - Richardson TX, US
Andrew Marshall - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01R 31/26

438 18, 3241581, 714731, 257 48, 257E2154

A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.

8379433, Feb 19, 2013

Sep 15, 2010

12/882355

Theodore W. Houston - Richardson TX, US
Makarand R. Kulkarni - Richardson TX, US
James (Hsu-Hsuan) Lan - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

G11C 11/24

365149, 36518914

A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a third transistor connected between the storage node and a write bit line having a third control element connected to a write word line. Additionally, the DRAM cell includes a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell. A method of operating an integrated circuit having a 3T DRAM cell includes providing a memory state on a storage node of the 3T DRAM cell and extending a refresh interval of the memory state with a supplemental capacitance added to the storage node.

8614143, Dec 24, 2013

Dec 3, 2008

12/327336

Makarand R. Kulkarni - Richardson TX, US
Deepak A. Ramappa - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/4763

438622, 438618, 257E21233, 216 39

One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

2007026, Nov 22, 2007

May 17, 2006

11/383853

Makarand R. Kulkarni - Richardson TX, US
Andrew Marshall - Dallas TX, US

Texas Instruments, Incorporated - Dallas TX

H01L 21/66

438 18

A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.

2022038, Dec 1, 2022

Oct 13, 2021

17/500086

- Dallas TX, US
Rajen Manicon Murugan - Dallas TX, US
Liang Wan - Chengdu, CN
Makarand Ramkrishna Kulkarni - Dallas TX, US
Jie Chen - Plano TX, US
Steven Alfred Kummerl - Carrollton TX, US

H01L 23/538
H01L 23/00
H01L 21/48

A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

2022020, Jun 30, 2022

Dec 30, 2020

17/138557

- Dallas TX, US
Makarand Ramkrishna Kulkarni - Dallas TX, US
Liang Wan - Chengdu, CN
Rajen Manicon Murugan - Dallas TX, US

H01Q 1/22
H01Q 9/04
H01L 23/367
H01L 23/31
H01L 23/538
H01L 23/66
H01L 23/00
H01L 21/48
H01L 21/56
H01L 21/683
H01P 3/08

An antenna in package (AIP) includes an IC die including bond pads and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer including a top dielectric layer , a top metal layer including an antenna , and a bottom layer including a bottom dielectric and a bottom metal layer including contact pads including a first contact pad , and filled vias . The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

2022018, Jun 9, 2022

May 28, 2021

17/334491

- Dallas TX, US
Makarand Ramkrishna KULKARNI - Dallas TX, US
Osvaldo Jorge LOPEZ - Annandale NJ, US
Yiqi TANG - Allen TX, US
Rajen Manicon MURUGAN - Dallas TX, US
Liang WAN - Chengdu, CN

H01L 23/498

In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

2023006, Mar 2, 2023

Aug 24, 2021

17/410535

- Dallas TX, US
Yiqi Tang - Allen TX, US
Jonathan Almeria Noquil - Plano TX, US
Makarand Ramkrishna Kulkarni - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01L 23/498
H01L 23/00
H01L 23/538
H01L 21/56
H01L 21/48
H01L 21/60

An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas and the second level having a second side with conductive landing pads. The electronic device includes a die with conductive terminals electrically coupled to respective ones of the landing areas, as well as solder balls attached to respective ones of the landing pads, and a package structure that encloses the die and a portion of the multilevel package substrate.