Paul Frank Marella, 625213 Eileen Dr, San Jose, CA 95129
Paul Marella Phones & Addresses
5213 Eileen Dr, San Jose, CA 95129 408-2182380
220 College Ave, Palo Alto, CA 94306 650-4971493
Stanford, CA
1239 Calle De Cuestanada, Milpitas, CA 95035 408-4971493
830 Montrose Ave, South Pasadena, CA 91030
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Professional/Technical
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Degree:
Graduate or professional degree
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Mentions for Paul Frank Marella
Publications & IP owners
Us Patents
Systems And Methods For Closed Loop Defect Reduction
US Patent:
7236847, Jun 26, 2007
Filed:
Jan 15, 2003
Appl. No.:
10/342819
Inventors:
Paul Frank Marella - San Jose CA, US
Assignee:
KLA-Tencor Technologies Corp. - Milpitas CA
International Classification:
G06F 17/50
H01L 21/00
H01L 21/00
US Classification:
700110, 205 82, 438 4, 438 12, 702 35, 716 4
Abstract:
Systems and methods for repairing defects on a specimen are provided. A method may include processing a specimen, detecting defects on the specimen, and repairing one or more of the defects. An additional method may include detecting defects on a specimen, repairing one or more of the defects, and inspecting the specimen to detect defects remaining on the specimen subsequent to repair. A system may include a process chamber, a measurement device configured to detect defects on a specimen, and a repair tool configured to repair one or more of the defects detected on the specimen. An additional system may include a measurement device, a repair tool, and an inspection tool configured to detect defects remaining on the specimen subsequent to repair. The systems may also include a processor configured to alter a parameter of an instrument coupled to the repair tool in response to output from the measurement device.
Electrical Process Monitoring Using Mirror-Mode Electron Microscopy
US Patent:
7514681, Apr 7, 2009
Filed:
Jun 13, 2006
Appl. No.:
11/451698
Inventors:
Paul F. Marella - San Jose CA, US
Mark A. McCord - Los Gatos CA, US
Marian Mankos - Palo Alto CA, US
David L. Adler - San Jose CA, US
Mark A. McCord - Los Gatos CA, US
Marian Mankos - Palo Alto CA, US
David L. Adler - San Jose CA, US
Assignee:
KLA-Tencor Technologies Corporation - Milpitas CA
International Classification:
H01L 21/02
H01J 37/145
G21K 7/00
H01J 37/145
G21K 7/00
US Classification:
250310, 250306, 250307, 25037008, 2504921, 324501, 324750, 324751, 324765
Abstract:
One embodiment relates to a method of inspecting a substrate using electrons. Mirror-mode electron-beam imaging is performed on a region of the substrate at multiple voltage differences between an electron source and a substrate, and image data is stored corresponding to the multiple voltage differences. A calculation is made of a measure of variation of an imaged aspect of a feature in the region with respect to the voltage difference between the electron source and the substrate. Other embodiments and features are also disclosed.
Methods And Systems For Inspection Of A Specimen Using Different Inspection Parameters
US Patent:
7738089, Jun 15, 2010
Filed:
Sep 3, 2004
Appl. No.:
10/933873
Inventors:
Steve R. Lange - Alamo VA, US
Paul Frank Marella - San Jose CA, US
Nat Ceglio - Pleasanton CA, US
Tao-Yi Fu - Fremont CA, US
Paul Frank Marella - San Jose CA, US
Nat Ceglio - Pleasanton CA, US
Tao-Yi Fu - Fremont CA, US
Assignee:
KLA-Tencor Technologies Corp. - Milpitas CA
International Classification:
G01N 21/00
US Classification:
3562371
Abstract:
Methods and systems for inspection of a specimen using different parameters are provided. One computer-implemented method includes determining optimal parameters for inspection based on selected defects. This method also includes setting parameters of an inspection system at the optimal parameters prior to inspection. Another method for inspecting a specimen includes illuminating the specimen with light having a wavelength below about 350 nm and with light having a wavelength above about 350 nm. The method also includes processing signals representative of light collected from the specimen to detect defects or process variations on the specimen. One system configured to inspect a specimen includes a first optical subsystem coupled to a broadband light source and a second optical subsystem coupled to a laser. The system also includes a third optical subsystem configured to couple light from the first and second optical subsystems to an objective, which focuses the light onto the specimen.
Methods And Systems For Inspection Of A Specimen Using Different Inspection Parameters
US Patent:
8384887, Feb 26, 2013
Filed:
Jun 8, 2010
Appl. No.:
12/796047
Inventors:
Steve R. Lange - Alamo CA, US
Paul Frank Marella - San Jose CA, US
Nat Ceglio - Pleasanton CA, US
Tao-Yi Fu - Fremont CA, US
Paul Frank Marella - San Jose CA, US
Nat Ceglio - Pleasanton CA, US
Tao-Yi Fu - Fremont CA, US
Assignee:
KLA-Tencor Technologies Corp. - Milpitas CA
International Classification:
G01N 21/00
US Classification:
3562371, 3562372, 3562375
Abstract:
Methods and systems for inspection of a specimen using different parameters are provided. One computer-implemented method includes determining optimal parameters for inspection based on selected defects. This method also includes setting parameters of an inspection system at the optimal parameters prior to inspection. Another method for inspecting a specimen includes illuminating the specimen with light having a wavelength below about 350 nm and with light having a wavelength above about 350 nm. The method also includes processing signals representative of light collected from the specimen to detect defects or process variations on the specimen. One system configured to inspect a specimen includes a first optical subsystem coupled to a broadband light source and a second optical subsystem coupled to a laser. The system also includes a third optical subsystem configured to couple light from the first and second optical subsystems to an objective, which focuses the light onto the specimen.
Methods And Systems For Inspection Of Wafers And Reticles Using Designer Intent Data
US Patent:
2005000, Jan 6, 2005
Filed:
Jul 1, 2004
Appl. No.:
10/883372
Inventors:
William Volk - San Francisco CA, US
James Wiley - Menlo Park CA, US
Sterling Watson - Palo Alto CA, US
Sagar Kekare - Plano TX, US
Carl Hess - Los Altos CA, US
Paul Marella - San Jose CA, US
Sharon McCauley - San Jose CA, US
Ellis Chang - Saratoga CA, US
James Wiley - Menlo Park CA, US
Sterling Watson - Palo Alto CA, US
Sagar Kekare - Plano TX, US
Carl Hess - Los Altos CA, US
Paul Marella - San Jose CA, US
Sharon McCauley - San Jose CA, US
Ellis Chang - Saratoga CA, US
International Classification:
G01N021/00
US Classification:
702108000
Abstract:
Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
Methods And Systems For Inspection Of Wafers And Reticles Using Designer Intent Data
US Patent:
2008008, Apr 3, 2008
Filed:
Nov 14, 2007
Appl. No.:
11/939983
Inventors:
Paul Marella - San Jose CA, US
Sharon McCauley - San Jose CA, US
Ellis Chang - Saratoga CA, US
William Volk - San Francisco CA, US
James Wiley - Menlo Park CA, US
Sterling Watson - Palo Alto CA, US
Sagar Kekare - Plano TX, US
Carl Hess - Los Altos CA, US
Sharon McCauley - San Jose CA, US
Ellis Chang - Saratoga CA, US
William Volk - San Francisco CA, US
James Wiley - Menlo Park CA, US
Sterling Watson - Palo Alto CA, US
Sagar Kekare - Plano TX, US
Carl Hess - Los Altos CA, US
International Classification:
H01L 21/66
US Classification:
438014000, 257E21521
Abstract:
Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
Stacked Devices For Multichip Modules
US Patent:
5804004, Sep 8, 1998
Filed:
May 24, 1996
Appl. No.:
8/655338
Inventors:
David B. Tuckerman - Dublin CA
Nicholas E. Brathwaite - Hayward CA
Paul Marella - Palo Alto CA
Kirk Flatow - San Jose CA
Nicholas E. Brathwaite - Hayward CA
Paul Marella - Palo Alto CA
Kirk Flatow - San Jose CA
Assignee:
nChip, Inc. - San Jose CA
International Classification:
H05K 332
US Classification:
156 60
Abstract:
A method for fabricating a multichip module includes attaching a first integrated circuit to a silicon circuit board. Bonding pads on the first integrated circuit are wire-bonded to a first set of contacts on the circuit board. A second integrated circuit is adhesively attached onto the top of the first integrated circuit. The second integrated circuit includes a recessed bottom surface to provide an overhang over the first integrated circuit which exposes the bonding pads on the top surface of the first integrated circuit. Then bonding pads on the second integrated circuit are wire-bonded to a second set of contacts on the circuit board.
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