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Paritosh R Kulkarni, 39Austin, TX

Related to:
Smita Chakraborty 42 Srikrishna M Kulkarni 58

Paritosh Kulkarni Phones & Addresses

Austin, TX   

Cedar Park, TX   

Cupertino, CA   

Milpitas, CA   

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Paritosh R Kulkarni

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Work

Company: Braves technologies llc Mar 2018 Position: Database qa engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: San Francisco State University 2010 to 2012 Specialities: Computer Science

Skills

Java • Xml • Web Services • Javascript • Testing • Test Automation • Microsoft Sql Server • Jquery • Oracle • Testng • C# • Vb.net • Visual Studio • Eclipse • Html • Software Quality Assurance • Agile Methodologies • Selenium Web Driver • Test Complete • Ms Sql • Bootsrap • Jenkins • Net Beans Ide • Oop • Data Structures • Web Development • Sql • Databases • Web Applications • Spring Framework • Tfs • Test Cases • Jira • Bugzilla • Mvc • Manual Testing • Quality Assurance • Test Planning • Quality Control • Software Development Life Cycle

Languages

Hindi • Marathi • English

Interests

Social Services • Children • Civil Rights and Social Action • Education • Environment • Poverty Alleviation • Science and Technology • Disaster and Humanitarian Relief • Human Rights • Animal Welfare • Health

Industries

Computer Software
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Paritosh Kulkarni resumes & CV records

Resumes

Paritosh Kulkarni Photo 21

Database Qa Engineer

Location:
12610 Riata Trace Pkwy, Austin, TX 78727
Industry:
Computer Software
Work:
Braves Technologies Llc
Database Qa Engineer Samsung Austin Semiconductor Dec 2015 - Jun 2016
Quality Assurance Engineer Strive Logistics Jun 2014 - Oct 2015
Software and Qa Developer Tivo Feb 2013 - Jul 2013
Qa Engineer Nextgentech, Llc Aug 2012 - Dec 2012
Contractor and Intern Nextgen Technician San Francisco State University Mar 2011 - Aug 2012
Student Assistant and It Specialist Cadreon Jun 2011 - Dec 2011
Computer Science Intern Cisco 2009 - 2010
Computer Science Intern De Anza College Sep 2007 - Apr 2009
English Writing and Speech Tutor Optimizers B.v. May 2005 - Jun 2006
Customer Sales Executive
Education:
San Francisco State University 2010 - 2012
Bachelors, Bachelor of Science, Computer Science De Anza College 2007 - 2010
Skills:
Java, Xml, Web Services, Javascript, Testing, Test Automation, Microsoft Sql Server, Jquery, Oracle, Testng, C#, Vb.net, Visual Studio, Eclipse, Html, Software Quality Assurance, Agile Methodologies, Selenium Web Driver, Test Complete, Ms Sql, Bootsrap, Jenkins, Net Beans Ide, Oop, Data Structures, Web Development, Sql, Databases, Web Applications, Spring Framework, Tfs, Test Cases, Jira, Bugzilla, Mvc, Manual Testing, Quality Assurance, Test Planning, Quality Control, Software Development Life Cycle
Interests:
Social Services
Children
Civil Rights and Social Action
Education
Environment
Poverty Alleviation
Science and Technology
Disaster and Humanitarian Relief
Human Rights
Animal Welfare
Health
Languages:
Hindi
Marathi
English

Publications & IP owners

Us Patents

Reconfigurable Data Packet Header Processor

US Patent:
2003011, Jun 26, 2003
Filed:
Dec 20, 2002
Appl. No.:
10/327223
Inventors:
Paritosh Kulkarni - San Jose CA, US
Nirmal Saxena - Los Altos CA, US
Assignee:
Chip Engines - Santa Clara CA
International Classification:
H04L012/28
US Classification:
370/392000
Abstract:
The present invention addresses the need for improved network data handling with a flexible, single point solution for packet header processing of data packets in a variable format transfer environment without associated performance or rate degradation. The present invention introduces a programmable or reconfigurable data packet header processor, wherein various registers (and ) of a chip are selectively programmed with a set of values that map the length () and location () of various header fields () to their position measured from the start of the packet (). Unlike dedicated hardware solutions, these updateable registers are designed to store length (), position () and type () data relating to multiple packet formats to improve extraction of packet header information by guiding the extraction to the exact point of the desired field information.

Reconfigurable Control Processor For Multi-Protocol Resilient Packet Ring Processor

US Patent:
2003017, Sep 18, 2003
Filed:
Jan 15, 2003
Appl. No.:
10/346035
Inventors:
Paritosh Kulkarni - San Jose CA, US
Roxanna Ganji - Fremont CA, US
Nirmal Saxena - Los Altos Hills CA, US
Assignee:
Chip Engines - Santa Clara CA
International Classification:
G06F015/173
US Classification:
709/236000, 709/237000, 709/238000, 709/224000
Abstract:
A method and system for adaptive multi-protocol resilient packet ring (RPR) processing are provided. The present invention provides optimal handling operations targeted for both legacy and evolving RPR functions related to topology discovery, fairness algorithms, and control-packet manipulation. Further, the present invention utilizes out-band paths, unique data and instruction memory constructs, and pipeline and multi-thread features to provide wire-rate performance. In one embodiment, a system of the present invention includes instruction memory; a fetch unit associated with instruction memory; a decode unit associated with the fetch unit; at least one execution unit associated with the decode unit; a load/store unit associated with the at least one execution unit; and data memory associated with the load/store unit.

Semiconductor With Hardware Locked Intellectual Property And Related Methods

US Patent:
2009008, Mar 26, 2009
Filed:
Sep 26, 2007
Appl. No.:
11/862154
Inventors:
Soumya BANERJEE - San Jose CA, US
Paritosh KULKARNI - San Jose CA, US
Assignee:
MIPS TECHNOLOGIES, INC. - Mountain View CA
International Classification:
G06F 12/14
H04L 9/00
US Classification:
380 46, 713194
Abstract:
A computer readable medium includes executable instructions to describe an intellectual property core with a key check mechanism configured to compare an external key with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.

Branch Prediction Based On Correlation Between Sets Of Bunches Of Branch Instructions

US Patent:
5896529, Apr 20, 1999
Filed:
Dec 24, 1997
Appl. No.:
8/998294
Inventors:
Paritosh M. Kulkarni - Campbell CA
Richard Reeve - Los Gatos CA
Nirmal R. Saxena - Los Altos Hills CA
Assignee:
Fujitsu Ltd.
International Classification:
G06F 938
US Classification:
395586
Abstract:
A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.

Predicting For All Branch Instructions In A Bunch Based On History Register Updated Once For All Of Any Taken Branches In A Bunch

US Patent:
6055629, Apr 25, 2000
Filed:
Jan 19, 1999
Appl. No.:
9/233695
Inventors:
Paritosh M. Kulkarni - Campbell CA
Richard Reeve - Los Gatos CA
Nirmal R. Saxena - Los Altos Hills CA
Assignee:
Fujitsu, Ltd.
International Classification:
G06F 938
US Classification:
712239
Abstract:
A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.

Method And Apparatus For A Single History Register Based Branch Predictor In A Superscalar Microprocessor

US Patent:
5742805, Apr 21, 1998
Filed:
Feb 15, 1996
Appl. No.:
8/601744
Inventors:
Paritosh M. Kulkarni - Campbell CA
Richard Reeve - Los Gatos CA
Nirmal R. Saxena - Los Altos Hills CA
Assignee:
Fujitsu Ltd. - Kawasaki
International Classification:
G06F 938
US Classification:
395586
Abstract:
Methods and apparati predict whether conditional branch computer instructions should be taken or not taken. A history register is maintained to record the history of groups of instructions, updated only once for each group. The history register and an address of one of the bytes of one of the instructions in each group are appended or otherwise combined to create an address to a table of two-bit saturating counters. The value of one of the bits of the counter at the address created is used for predicting all the conditional branch instructions for each branch in the group.

Possible Relatives

David S Kulkarni  Deepa Kulkarni  Deepak V Kulkarni  Deepti M Kulkarni  Dhananjay D Kulkarni  Dhiraj P Kulkarni  Dilip Kulkarni  Paritosh R Patel  Paritosh Das 

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