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Peggy Jo Irelan, 49973 Fieldstone Pl, Chandler, AZ 85249

Known as:
Peggy J Irelan Peggy Living Irelan Peggy Jo Irelan Living Peggy Ireland Jo Irelan Peggy
Related to:
Ivan A Ireland 57

Peggy Irelan Phones & Addresses

973 Fieldstone Pl, Chandler, AZ 85249    602-7903521   

2710 Megan St, Chandler, AZ 85224    480-6641034   

5932 Mercury Way, Chandler, AZ 85226   

Colchester, VT   

Williams, AZ   

Ash Fork, AZ   

Phoenix, AZ   

Coronado, AZ   

Maricopa, AZ   

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Peggy Jo Irelan

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Work

Company: Intel corporation Jan 2016 to Oct 2016 Position: Iot technology strategist

Education

Degree: Bachelors, Bachelor of Science In Civil Engineering School / High School: Purdue University 1993 to 1997 Specialities: Mathematics

Skills

System Architecture • Debugging • Software Engineering • Software Development • Computer Architecture • Device Drivers • Embedded Systems • Intel • Soc • Semiconductors • C • Microarchitecture • Microprocessors • Operating Systems • Cross Functional Team Leadership • Performance Tuning • Algorithms • Embedded Software • Firmware • Perl • Software Design • Asic • Hardware Architecture • Performance Measurement • Systems Analysis • Performance Metrics • High Performance Computing • Cloud Computing • Distributed Systems • Ia Assembly • Optimization Software • Multi Core Optimization • Intel Processor Architecture • Processors • Integration • C++ • Architecture • Sw Debugging • Multi Core Programming • Power Analysis • Linux • Hardware • Product Management • Program Management • Application Specific Integrated Circuits • System on A Chip • Leadership • Product Development • Organizational Leadership

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Semiconductors
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Peggy Irelan resumes & CV records

Resumes

Peggy Irelan Photo 15

Intel Fellow

Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Intel Corporation Jan 2016 - Oct 2016
Iot Technology Strategist Intel Corporation Jan 2016 - Oct 2016
Intel Fellow Intel Corporation Feb 2015 - Jan 2016
Senior Principal Engineer, Director and Cto, Iot Intelligent Software Platforms and Analytics Intel Corporation Apr 2008 - Sep 2013
Principal Engineer, Chief Platform Monitoring Engineer Intel Corporation Aug 2002 - Apr 2008
Software Engineer Intel Corporation Jun 2000 - Aug 2002
Software Application Engineer Motorola May 1999 - May 2000
Sensor Products Division System Engineer Motorola Apr 1998 - May 1999
Software Engineer
Education:
Purdue University 1993 - 1997
Bachelors, Bachelor of Science In Civil Engineering, Mathematics Hillwood High School
Skills:
System Architecture, Debugging, Software Engineering, Software Development, Computer Architecture, Device Drivers, Embedded Systems, Intel, Soc, Semiconductors, C, Microarchitecture, Microprocessors, Operating Systems, Cross Functional Team Leadership, Performance Tuning, Algorithms, Embedded Software, Firmware, Perl, Software Design, Asic, Hardware Architecture, Performance Measurement, Systems Analysis, Performance Metrics, High Performance Computing, Cloud Computing, Distributed Systems, Ia Assembly, Optimization Software, Multi Core Optimization, Intel Processor Architecture, Processors, Integration, C++, Architecture, Sw Debugging, Multi Core Programming, Power Analysis, Linux, Hardware, Product Management, Program Management, Application Specific Integrated Circuits, System on A Chip, Leadership, Product Development, Organizational Leadership

Publications & IP owners

Us Patents

Method, Apparatus, And System For Speculative Execution Event Counter Checkpointing And Restoring

US Patent:
2012022, Sep 6, 2012
Filed:
Feb 2, 2012
Appl. No.:
13/365104
Inventors:
Laura A. Knauth - Portland OR, US
Ravi Rajwar - Portland OR, US
Peggy J. Irelan - Chandler AZ, US
Martin G. Dixon - Portland OR, US
Konrad K. Lai - Vancouver WA, US
International Classification:
G06F 9/44
US Classification:
718100
Abstract:
An apparatus, method, and system are described herein for providing programmable control of performance/event counters. An event counter is programmable to track different events, as well as to be checkpointed when speculative code regions are encountered. So when a speculative code region is aborted, the event counter is able to be restored to it pre-speculation value. Moreover, the difference between a cumulative event count of committed and uncommitted execution and the committed execution, represents an event count/contribution for uncommitted execution. From information on the uncommitted execution, hardware/software may be tuned to enhance future execution to avoid wasted execution cycles.

Method And Apparatus For Obtaining A Call Stack To An Event Of Interest And Analyzing The Same

US Patent:
2012031, Dec 6, 2012
Filed:
May 31, 2011
Appl. No.:
13/118766
Inventors:
Michael W. Chynoweth - Rio Rancho NM, US
Peggy J. Irelan - Chandler AZ, US
Matthew C. Merten - Hillsboro OR, US
Seung-Woo Kim - Dupont WA, US
Laura A. Knauth - Portland OR, US
Stanislav Bratanov - Nizhniy Novgorod, RU
International Classification:
G06F 9/38
US Classification:
712234, 712E09045
Abstract:
In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

Last Branch Record Indicators For Transactional Memory

US Patent:
2013017, Jul 11, 2013
Filed:
Mar 6, 2013
Appl. No.:
13/786724
Inventors:
RAVI RAJWAR - Portland OR, US
PETER LACHNER - Heroldstatt, DE
LAURA KNAUTH - Portland OR, US
KONRAD LAI - Vancouver WA, US
PEGGY IRELAN - Chandler AZ, US
International Classification:
G06F 9/38
US Classification:
712234
Abstract:
In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Performance Monitoring Resources Programmed Status

US Patent:
2013033, Dec 12, 2013
Filed:
Dec 28, 2011
Appl. No.:
13/995566
Inventors:
Laura A. Knauth - Portland OR, US
Peggy J. Irelan - Chandler AZ, US
International Classification:
G06F 9/54
US Classification:
718102
Abstract:
A system and method for a performance monitoring hardware unit that may include logic to poll one or more performance monitoring shared resources and determine a status of each performance monitoring shared resource. The performance monitoring hardware unit may also include an interface to provide the status to allow programming of the one or more performance monitoring shared resource. The status may correspond to a usage and/or an errata condition. Thus, the performance monitoring hardware unit may prevent programming conflicts of the one or more performance monitoring shared resources.

Causing An Interrupt Based On Event Count

US Patent:
2014001, Jan 9, 2014
Filed:
Dec 29, 2011
Appl. No.:
13/991878
Inventors:
Ahmad Yasin - Haifa, IL
Peggy J. Irelan - Chandler AZ, US
Ofer Levy - Atlit, IL
Emile Ziedan - Yamma-Zimer, IL
Grant Zhou - Chandler AZ, US
International Classification:
G06F 9/38
US Classification:
712244
Abstract:
Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

Event Counter Checkpointing And Restoring

US Patent:
2011016, Jun 30, 2011
Filed:
Dec 26, 2009
Appl. No.:
12/655204
Inventors:
Laura A. Knauth - Portland OR, US
Ravi Rajwar - Beaverton OR, US
Konrad K. Lai - Vancouver WA, US
Martin G. Dixon - Portland OR, US
Peggy Irelan - Chandler AZ, US
International Classification:
G06F 9/312
G06F 9/38
US Classification:
712228, 712239, 712E09033, 712E09045, 711105
Abstract:
A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods are also disclosed. Apparatus, systems, and machine-readable medium having software are also disclosed.

Microservice Provision And Management

US Patent:
2022031, Oct 6, 2022
Filed:
Mar 18, 2022
Appl. No.:
17/698418
Inventors:
- Santa Clara CA, US
Peggy Jo Irelan - Chandler AZ, US
Hassnaa Moustafa - San Jose CA, US
International Classification:
G06F 9/50
H04L 67/10
H04L 67/12
Abstract:
A compute system that includes an Internet of things (IoT) device is provided. The IoT device includes a common services interface (CSI) to create a self-managing network of devices with other nodes comprising the CSI.

Microservice Provision And Management

US Patent:
2020005, Feb 13, 2020
Filed:
Jun 27, 2017
Appl. No.:
16/478593
Inventors:
- Santa Clara CA, US
Peggy J. Irelan - Chandler AZ, US
Hassnaa Moustafa - Portland OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
G06F 9/50
H04L 29/08
Abstract:
A compute system that includes an Internet of things (IoT) device is provided. The IoT device includes a common services interface (CSI) to create a self-managing network of devices with other nodes comprising the CSI.

Possible Relatives

David K Irelan  Dennis C Irelan  Donald Irelan  Edward A Irelan  Eric S Irelan  Heather J Irelan  Jeri C Irelan  Peggy J Johnson  Peggy L Standifer  Peggy L Johnston 

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