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Amul D Desai, 37San Jose, CA

Known as:
Amul D Desal

Amul Desai Phones & Addresses

San Jose, CA   

Sunnyvale, CA   

Milpitas, CA   

Fremont, CA   

Austin, TX   

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Resumes

Amul Desai Photo 21

Principal Engineer

Location:
Milpitas, CA
Industry:
Semiconductors
Work:
Sandisk
Principal Engineer Sandisk Feb 2015 - Aug 2018
Principal Design Engineer Sandisk Jun 2012 - Feb 2015
Design Engineer Ii Amd Jan 2012 - May 2012
Co-Op Engineer Follett Higher Education Group Jan 2011 - Jan 2012
Team Lead and System Support Idea Cellular Ltd Dec 2009 - Apr 2010
Intern
Education:
Arizona State University 2010 - 2012
Master of Science, Masters, Electrical Engineering, Engineering Dharmsinh Desai University 2006 - 2010
Bachelor of Engineering, Bachelors, Communication, Electronics Best High School, Ahmedabad 2006
Skills:
Verilog, Vlsi, C++, C, Computer Architecture, Vhdl, Analog Circuit Design, Fpga, Microprocessors, Modelsim, Systemverilog, Asic, Embedded Systems, Cadence Virtuoso, Rtl Design, Circuit Design, Sram, Memory Test, Debugging, System Verification, Static Timing Analysis, Eeprom, Cadence, Low Power Design, Mixed Signal, Integrated Circuit Design, Ruby, Memory Design, Nand Flash, Tcl, Eda, Very Large Scale Integration, Vlsi Design, Low Power Design, High Speed Design, Cmos
Languages:
English
Hindi
Gujarati
Amul Desai Photo 22

Amul Desai

Amul Desai Photo 23

Amul Desai

Amul Desai Photo 24

Authorised Person At Omni Associates

Location:
Bhvnagar Area, India
Industry:
Staffing and Recruiting

Publications & IP owners

Us Patents

Column Erasing In Non-Volatile Memory Strings

US Patent:
2020001, Jan 9, 2020
Filed:
Jan 18, 2019
Appl. No.:
16/252300
Inventors:
- Addison TX, US
Amul Dhirajbhai Desai - Milpitas CA, US
Ankitkumar Babariya - San Jose CA, US
International Classification:
G11C 16/16
G11C 16/04
Abstract:
Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.

First Read Countermeasures In Memory

US Patent:
2018025, Sep 6, 2018
Filed:
Nov 17, 2017
Appl. No.:
15/816546
Inventors:
- Plano TX, US
Idan Alrod - Herzliya, IL
Amul Desai - Milpitas CA, US
Jun Wan - San Jose CA, US
Ken Cheah - San Jose CA, US
Assignee:
SanDisk Technologies LLC - Plano TX
International Classification:
G11C 16/34
G11C 16/16
G11C 16/26
Abstract:
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

Possible Relatives

Daxa M Desai  Daksha A Desai  Aakash R Desai  Deepa A Desai  Deepak N Desai  Deepika H Desai  Darshak R Desai 

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