Rakesh B Sethi, 6514930 Farwell Ave, Saratoga, CA 95070

6586806, Jul 1, 2003

Sep 3, 1997

08/929308

Sheng Yueh Pai - Saratoga CA
Fredrick B. Jenne - Los Gatos CA
Rakesh B. Sethi - Campbell CA

Cypress Semiconductor Corporation - San Jose CA

H01L 2976

257401, 257389

A transistor includes a non-self-aligned gate-terminal junction in a substrate having a relatively thick oxide layer disposed between a gate region and a terminal region and a relatively thin oxide layer disposed between the gate structure and the substrate. The terminal region may be the drain region of the transistor and it may include a buried N+ region within the substrate. The transistor may be formed in a p-well. Further, the transistor may also include a self-aligned gate-terminal junction between the gate structure and a source region. In a further embodiment, a transistor fabrication method includes forming an active area in a substrate and implanting an N-type impurity into a first terminal region of the active area. An oxide layer is differentially grown over the active area so that the oxide layer has a first thickness over the first terminal region and a second thickness over the remaining portion of the active area. The first thickness is substantially thicker than the second thickness and, in some embodiments, may be up to twice as thick as the second thickness.

5760438, Jun 2, 1998

Feb 4, 1997

8/800656

Rakesh Balraj Sethi - Campbell CA
Christopher S. Norris - Morgan Hill CA
Genda J. Hu - Sunnyvale CA

Cypress Semiconductor Corporation - San Jose CA

H01L 29788

257317

A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts. The erase node includes a buried N+ drain region in a P-type substrate, a buried implant plate doped N-type adjacent the drain region in the substrate, a tunnel oxide disposed over at least a portion of the plate and the drain region, the tunnel oxide extending into and abutting a gate oxide region, and thence to a field oxide region in a relaxed fashion, a polycrystalline silicon floating gate disposed over the field oxide, gate oxide, and tunnel oxide regions, a sandwich of ONO on the floating gate, and a polycrystalline silicon control gate (poly 2) disposed on the ONO. Programming occurs through the programming transistor. Reading occurs through a read path including the read transistor.

5284786, Feb 8, 1994

Aug 14, 1992

7/930311

Rakesh B. Sethi - Campbell CA

National Semiconductor Corporation - Santa Clara CA

H01L 21336

437 43

A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400. ANG. thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100. ANG. thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600. ANG. thick, a silicon dioxide layer about 20-50. ANG. thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000. ANG. thick formed on the silicon dioxide layer.

5780889, Jul 14, 1998

Nov 22, 1995

8/562183

Rakesh B. Sethi - Campbell CA

Cypress Semiconductor Corp. - San Jose CA

H01L 2976
H01L 29788

257316

The presently preferred embodiment of the invention provides a memory structure that eliminates the thick gate associated with the offset of the FAMOS transistor and reduces the standard 225 angstrom offset to a 100 angstrom offset required for FN tunnelling. The 100 angstrom offset is realized uniformly underneath the entire area of the floating poly. The invention uses transistors each having a 100 angstrom offset to realize both erase and programming functions. The present invention realizes an erasing feature through an erase transistor and an ERL line. However, the programming of the cell will be realized through the programming transistor. As a result, a double poly flash cell will function like an EEPROM. This functioning eliminates the hot electron tunnelling required to program conventional double poly flash cells and results in a significant reduction in chip real estate. The reduction allows the present invention to be scaled to next generation architectures.

5844271, Dec 1, 1998

Aug 21, 1995

8/517495

Rakesh Sethi - Campbell CA
Wenchi Ting - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

H01L 29788

257318

An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used. The voltages applied to the N-plate region are capacitively coupled to the floating gate.

5648669, Jul 15, 1997

May 26, 1995

8/452217

Rakesh Balraj Sethi - Campbell CA
Christopher S. Norris - Morgan Hill CA
Genda J. Hu - Sunnyvale CA

Cypress Semiconductor - San Jose CA

H01L 29788
H01L 2976

257318

A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts. The erase node includes a buried N+ drain region in a P-type substrate, a buried implant plate doped N-type adjacent the drain region in the substrate, a tunnel oxide disposed over at least a portion of the plate and the drain region, the tunnel oxide extending into and abutting a gate oxide region, and thence to a field oxide region in a relaxed fashion, a polycrystalline silicon floating gate disposed over the field oxide, gate oxide, and tunnel oxide regions, a sandwich of ONO on the floating gate, and a polycrystalline silicon control gate (poly 2) disposed on the ONO. Programming occurs through the programming transistor. Reading occurs through a read path including the read transistor.

5432749, Jul 11, 1995

Apr 26, 1994

8/233057

Rakesh B. Sethi - Campbell CA

National Semiconductor Corporation - Santa Clara CA

G11C 1600

365218

An arrangement for reducing the erratic operation of a non-volatile memory cell caused by the accumulation of holes at a specific location within the cell during the electrical erasing of the cell includes a layer of hole confinement material positioned at the specific location the holes accumulate for containing the holes in a specific area. The arrangement also includes an arrangement for removing the holes from the containment area. A method of reducing the erratic operation of a non-volatile memory cell caused by the accumulation of holes at a specific location within the cell during the electrical erasing of the cell includes the step of providing a layer of hole confinement material positioned at the specific location the holes accumulate for containing the holes in the layer of hole confinement material.

5573973, Nov 12, 1996

Nov 14, 1994

8/339970

Rakesh B. Sethi - Campbell CA

National Semiconductor Corporation - Santa Clara CA

H01L 2176

437 67

An integrated circuit based on submicron technology is disclosed herein along with the way in which it is formed. The integrated circuit is comprised of an arrangement of different substances which are combined to form its body structure and which define within the body structure an array of electronic components including a diamond thin film coated trench arrangement. In one embodiment disclosed herein, the array of electronic component includes two such components which are in close proximity to and must be electrically isolated from one another and the diamond thin film coated trench arrangement serves to electrically isolate these two components from each other. In a second embodiment, the diamond thin film coated trench is specifically designed to serve as a capacitor forming part of, for example, a DRAM, a mixed signal circuit or a neuro-fuzzy circuit.