Sean Shaohua Chen, 651029 Big Oak Flat Ct, Las Vegas, NV 89138

6404266, Jun 11, 2002

Jul 25, 2000

09/624738

Sean S. Chen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 1760

327478, 327 53, 327563

A differential input stage with full-rail sensing and reduced latch-up susceptibility includes an emitter-coupled pair, a current mirror, and several series resistors. For a NPN emitter-coupled pair, a series resistor is connected between the input node and the base of each transistor of the emitter-coupled pair, and a series resistor is connected between each load resistor and its corresponding current mirror transistor. The series resistors reduce current flowing into the PN junctions when power to the overall circuit is disabled but an input signal is present at the input terminals.

6433516, Aug 13, 2002

Jun 11, 2001

09/879474

Sean S. Chen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H02J 716

320150

A temperature stabilized, constant current source capable of charging a fully discharged battery of the present invention includes a feedback control stage that provides a substantially constant battery charging current at a particular temperature. A temperature stabilized current source stage coupled to a bias resistor includes a negative temperature coefficient current source that provides a countervailing control current to a positive temperature coefficient current source that is coupled from a sensing resistor. The temperature dependencies of the positive and negative temperature coefficient current sources tend to cancel each other out so as to provide a temperature stabilized current to the sensing resistor. The bias resistor provides a bias current to the temperature stabilized current source stage in such a way that the temperature stabilized current source stage provides a charging current to a fully discharged battery.

6621333, Sep 16, 2003

Dec 11, 2001

10/014728

Sean S. Chen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03F 102

330 9, 330256, 330265, 327307

A circuit for countering offset voltage in an amplifier induced by changes in the output load. The circuit comprises an input stage, an output stage, and first and second current compensation stages. The first current compensation stage is coupled to the output stage and produces a first compensation current that is a function of the output current. The input stage is coupled to the first current compensation stage from which it receives the first compensation current. The input stage is configured to cause a change in the voltage between its input terminals in response to the first compensation current. The second current compensation stage produces a second compensation current, which is also fed into the input stage to act jointly with the first compensation current. The first compensation current may be linearly related to the output current. The second compensation current may be exponentially related to the output current.

6788143, Sep 7, 2004

Apr 29, 2002

10/136196

Sean S. Chen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03F 345

330253, 330311

A cascode stage is arranged to improve performance of an operational amplifier. The cascode stage includes transistors that are arranged to operate as a current mirror. Each side of the current mirror has a corresponding voltage at a corresponding node. One of the corresponding nodes corresponds to a high impedance node that is coupled to a subsequent stage of the amplifier. The voltages at the corresponding nodes are closely matched to one another such that the input referred offset in the amplifier is minimized and the power supply rejection ratio is improved (PSRR). A transistor threshold voltage and a transistor saturation voltage determine the headroom requirements of the cascode stage, such that low power supply voltage operation is possible. The biasing of the transistors in the cascode stage is simplified such that minimal biasing circuitry is required, and overall power consumption may be minimized.

6819164, Nov 16, 2004

Oct 17, 2002

10/274313

Sean S. Chen - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

G05F 110

327540, 327543, 327404, 323312, 323313, 323315

A circuit is arranged to enable bi-directional trimming of a reference voltage. A trim current is generated by mirroring a bias current using one or more selectable current source circuits. The selectable current source circuits may each contain transistors that are sized differently from corresponding transistors of the other selectable current source circuits. The sizing may be arranged in a binary chain such that a range of currents may be generated for the trim current while allowing for selection of the level of adjustment for the reference voltage. The current selected for the trim current depends on which of the selectable current sources is enabled. The node corresponding to the trim current is selectively coupled to a load to either increase the voltage across the load or decrease the voltage across the load, providing bi-directional trimming of the reference voltage measured across the load.

6914494, Jul 5, 2005

Aug 26, 2003

10/649085

Sean S. Chen - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

H03L007/00

331111, 143185, 143173

A low current oscillator circuit comprising a comparator for driving an output signal. A first capacitor chain is coupled to the comparator. The first capacitor chain is configured for setting a first input voltage of the comparator. A second capacitor chain is also coupled to the comparator. The second capacitor chain is configured for setting a second input voltage of the comparator, wherein the first capacitor chain and the second capacitor chain determine a first voltage level and a second voltage level of oscillation of the comparator. The first capacitor chain and the second capacitor chain are free of DC current flow.

7400187, Jul 15, 2008

Oct 2, 2001

09/970297

Sean S. Chen - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

G05F 1/10

327539, 323313

The present invention relates to a low impedance band-gap voltage reference circuit which comprises a band-gap reference circuit, a buffer circuit to reduce the impedance and related noise associated with band-gap references electronically coupled with the band-gap voltage reference circuit and a voltage pull-up device electronically coupled with both the band-gap reference circuit and the buffer circuit. The voltage pull-up device acts to reduce the supply voltage required to maintain a stable, low Z band-gap reference voltage.

7440933, Oct 21, 2008

Jun 18, 2004

10/871143

Alexander Abrashkevich - Toronto, CA
Dmitri Abrashkevich - Toronto, CA
John H. Bailey - Durham NC, US
Sean Chen - Fremont CA, US
James B. Cottingham - Fuquay-Varina NC, US
Michael Peter Etgen - Cary NC, US
Vijaya Ratnala - Austin TX, US
Frederick O. G. van Veen - Richmond Hill, CA
Michael LaVerne Wamboldt - Garner NC, US
Mark Francis Wilding - Barrie, CA

International Business Machines Corporation - Armonk NY

G06F 17/00
G06N 5/02
G06N 5/00

706 46, 706 45

Disclosed is a data processing system-implemented method. The data processing system-implemented method includes configuring a symptom pathway that leads to a solution, and associating a usage indicator with the symptom pathway, the usage indicator indicating a frequency in which the symptom pathway was previously implemented for successfully resolving previously experienced problems.