Tong Chen, 48Philadelphia, PA

7784037, Aug 24, 2010

Apr 14, 2006

11/279768

Tong Chen - Yorktown Heights NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US
Byoungro So - Santa Clara CA, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Duluth GA, US

International Business Machines Corporation - Armonk NY

G06F 9/45

717143

A compiler implemented software cache is provided in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.

8006238, Aug 23, 2011

Sep 26, 2006

11/535172

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US
Tong Chen - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

G06F 9/45
G06F 9/40
G06F 9/46

717150, 717149, 717160, 712204, 718102, 718104

A process, compiler, computer program product and system for workload partitioning in a heterogeneous system. The process includes determining heterogeneous alignment constraints in the workload, partitioning a portion of tasks to a processing element sensitive to alignment constraints, and partitioning a remaining portion of tasks to a processing element not sensitive to alignment constraints.

8055849, Nov 8, 2011

Apr 4, 2008

12/062587

Tong Chen - Yorktown Heights NY, US
Marc Gonzalez tallada - Yorktown Heights NY, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

G06F 12/12

711136, 711137, 711E12002, 712207

Reducing cache pollution of a software controlled cache is provided. A request is received to prefetch data into the software controlled cache. A first designator is set for a first cache access to a first value. If there is the second cache access to prefetch, a determination is made as to whether data associated with the second cache access exists in the software controlled cache. If the data is in the software controlled cache, a determination is made as to whether a second value of a second designator is greater than the first value of the first cache access. If the second value fails to be greater than the first value, the position of the first cache access and the second cache access in a cache line is swapped. The first value is decremented by a predetermined amount and the second value is replaced to equal the first value.

8146064, Mar 27, 2012

Apr 4, 2008

12/062559

Tong Chen - Yorktown Heights NY, US
Marc Gonzalez tallada - Yorktown Heights NY, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

G06F 9/45

717141, 717140, 717150, 717151, 717153, 711113, 711118, 711213, 711E12002

Dynamically controlling a prefetching range of a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain irregular memory references. For each irregular memory reference in the source code, the compiler determines whether the irregular memory reference is a candidate for optimization. Responsive to identifying an irregular memory reference that may be optimized, the complier determines whether the irregular memory reference is valid for prefetching. If the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library to dynamically prefetch the irregular memory references. Data associated with the irregular memory references are dynamically prefetched into the software controlled cache when the runtime library call is invoked.

8214816, Jul 3, 2012

May 28, 2008

12/128194

Tong Chen - Yorktown Heights NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US
Byoungro So - Santa Clara CA, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Duluth GA, US

International Business Machines Corporation - Armonk NY

G06F 9/45

717157

A compiler implemented software cache in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.

8239841, Aug 7, 2012

Apr 4, 2008

12/062579

Tong Chen - Yorktown Heights NY, US
Marc Gonzalez tallada - Yorktown Heights NY, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

G06F 9/44

717140

Prefetching irregular memory references into a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain an irregular memory reference. The compiler determines if the irregular memory reference within the at least one loop is a candidate for optimization. Responsive to an indication that the irregular memory reference may be optimized, the compiler determines if the irregular memory reference is valid for prefetching. Responsive to an indication that the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library for the irregular memory reference. Data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked.

8281295, Oct 2, 2012

May 23, 2008

12/125982

Tong Chen - Yorktown Heights NY, US
Haibo Lin - Beijing, CN
John K. O'Brien - South Salem NY, US
Tao Zhang - Duluth GA, US

International Business Machines Corporation - Armonk NY

G06F 9/45

717151, 711147

Compiler analysis and runtime coherency checking for reducing coherency problems is provided. Source code is analyzed to identify at least one of a plurality of loops that contains a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by at least one of a software controlled cache or a direct buffer. A determination is made as to whether there is a data dependence between the memory reference and at least one reference from at least one of other direct buffers or other software controlled caches in response to an indication that the memory reference is an access to the global memory that should be handled by either the software controlled cache or the direct buffer. A direct buffer transformation is applied to the memory reference in response to a negative indication of the data dependence.

8285670, Oct 9, 2012

Jul 22, 2008

12/177507

Tong Chen - Yorktown Heights NY, US
John K. O'Brien - South Salem NY, US
Tao Zhang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

G06F 7/00

707609, 717141, 711117

Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.