BackgroundCheck.run
Search For

Ken Cheong Cheah, 571324 Clayton Rd, San Jose, CA 95127

Ken Cheah Phones & Addresses

1324 Clayton Rd, San Jose, CA 95127   

Las Vegas, NV   

Sunnyvale, CA   

Santa Clara, CA   

Foster City, CA   

1508 Bedford Ave, Sunnyvale, CA 94087   

Social networks

Ken Cheong Cheah

Linkedin

Work

Company: Eon silicon solutions, inc May 2005 Position: Director of design engineering

Education

School / High School: University Science Malaysia- Penang, MY Aug 1995 Specialities: MBA in Business Management

Skills

Design architect • project management • people development

Mentions for Ken Cheong Cheah

Resumes & CV records

Resumes

Ken Cheah Photo 27

Ken Cheah

Ken Cheah Photo 28

Ken Cheah - Sunnyvale, CA

Work:
Eon Silicon Solutions, Inc May 2005 to 2000
Director of Design Engineering
Spansion Penang, Malaysia - Penang, MY Aug 1998 to Apr 2005
Department Manager
Intel Penang, Malaysia - Penang, MY May 1991 to Jul 1998
Senior Design Engineer
Education:
University Science Malaysia - Penang, MY Aug 1995 to Apr 1998
MBA in Business Management
University Malaya - Kuala Lumpur Aug 1987 to Apr 1991
Bachelor of Electrical Engineering
Skills:
Design architect, project management, people development

Publications & IP owners

Us Patents

Two-Stage Pipeline Sensing For Page Mode Flash Memory

US Patent:
6243291, Jun 5, 2001
Filed:
Feb 15, 2000
Appl. No.:
9/504186
Inventors:
Ken C. Cheah - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1134
US Classification:
36518512
Abstract:
A method for operating a page mode memory device includes decoding an address defining a page for access and sensing first data on a first portion of the page. The first data is then produced at an output. Substantially simultaneously, second data is sensed on a second portion of the page and subsequently the second data is produced at the output. In this manner, the current drain and noise within the memory device are reduced to improve performance and reliability of the memory device.

First Read Countermeasures In Memory

US Patent:
2018025, Sep 6, 2018
Filed:
Nov 17, 2017
Appl. No.:
15/816546
Inventors:
- Plano TX, US
Idan Alrod - Herzliya, IL
Amul Desai - Milpitas CA, US
Jun Wan - San Jose CA, US
Ken Cheah - San Jose CA, US
Assignee:
SanDisk Technologies LLC - Plano TX
International Classification:
G11C 16/34
G11C 16/16
G11C 16/26
Abstract:
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.