Utpal Desai resumes & CV records
Resumes
Utpal Desai
Utpal N Desai, 571925 Cape Hilda Pl, San Jose, CA 95133
Utpal Desai Phones & Addresses
1925 Cape Hilda Pl, San Jose, CA 95133 408-9293535
947 E Aster Ave, Palatine, IL 60074 847-9172523
Fremont, CA
Santa Clara, CA
Washington, DC
Hayward, CA
Dekalb, IL
1925 Cape Hilda Pl, San Jose, CA 95133 619-7426797
Work
Position:
Food Preparation and Serving Related Occupations
Education
Degree:
High school graduate or higher
Emails
Mentions for Utpal N Desai
Publications & IP owners
Us Patents
Power Supply Voltage Droop Compensated Clock Modulation For Microprocessors
US Patent:
7409568, Aug 5, 2008
Filed:
Jul 5, 2006
Appl. No.:
11/481717
Inventors:
Simon M. Tam - Redwood City CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03B 19/00
US Classification:
713322, 713300, 713310, 713320, 713321, 713323, 713324, 713330, 713340, 713401, 713600, 713601, 327114, 327361
Abstract:
A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
Power Supply Voltage Droop Compensated Clock Modulation For Microprocessors
US Patent:
2005002, Jan 27, 2005
Filed:
Jul 25, 2003
Appl. No.:
10/627272
Inventors:
Simo Tam - Redwood City CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
International Classification:
G06F001/26
US Classification:
713323000
Abstract:
A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
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