Vimal R Patel, 52Geneva, IL

2014000, Jan 2, 2014

Jun 28, 2012

13/535802

Chihhung Liao - Fremont CA, US
Phu Nguyen - Dublin CA, US
Vimal R. Patel - Rochester MN, US
George F. Paulik - Rochester MN, US
Peder J. Paulson - Rochester MN, US
Brian J. Reed - Rochester MN, US
Salvatore N. Storino - Rochester MN, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G11C 17/16
G06F 17/50

365 96, 716100

An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.

6476659, Nov 5, 2002

Nov 21, 2001

09/990467

Vimal Ramannhai Patel - Rochester MN
Curtis Walter Preuss - Rochester MN
Daniel Guy Young - Rochester MN

International Business Machines Corporation - Armonk NY

H03K 190185

327333, 326 81

A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.

2016029, Oct 6, 2016

Apr 1, 2015

14/676523

- Atlanta GA, US
James Compton - Elgin IL, US
Rajeev Singh - Fairfax VA, US
Vimal Patel - Morganville NJ, US

H04L 12/851
H04W 12/06
H04L 29/06

A single cellular radio is enabled to support multiple phone lines and data service. The system can be split into two parts: a telephone adapter that receives input from one or more phone lines, and a wireless hot spot communicably coupled to one or more telephone adapters that transmits communications associated with the phone lines and data service to the mobile network. The telephone adapter can include phone jacks, WiFi, and LAN connections and also some traffic management functionality that routes voice traffic to higher class of services than non-voice data. The wireless hotspot can then map communications with higher classes of service to dedicated bearers with guaranteed bitrates, and the lower classes of service to dedicated bearers with non-guaranteed bitrates or even default bearers.

2014025, Sep 11, 2014

Mar 5, 2013

13/784980

- Armonk NY, US
Phil C. Paone - Rochester MN, US
Vimal R. Patel - Rochester MN, US
Gregory J. Uhlmann - Rochester MN, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01H 85/05
G06F 17/50

327525, 716119

Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.