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Vipulkumar B Patel5402 SW 40Th Cir, Ocala, FL 34474

Known as:
Vipul Patel Vipulkuma B Patel
Related to:
Brayan J Patel 32 Amratlal N Patel 78

Vipulkumar Patel Phones & Addresses

Ocala, FL   

Franklinville, NJ   

Macon, GA   

Oak Forest, IL   

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Career records & work history

Medicine Doctors

Vipulkumar G. Patel

Specialties:
Internal Medicine
Work:
Vipulkumar G Patel MD PA
3828 Hughes Ct STE 105, Dickinson, TX 77539
281-5348800 (phone) 281-5348826 (fax)
Education:
Medical School
Baroda Medical College, Gujarat, India
Graduated: 1992
Conditions:
Acute Upper Respiratory Tract Infections, Anxiety Phobic Disorders, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Hypertension (HTN), Hypothyroidism, Iron Deficiency Anemia, Overweight and Obesity, Abnormal Vaginal Bleeding, Acute Bronchitis, Acute Pharyngitis, Acute Sinusitis, Anemia, Atrial Fibrillation and Atrial Flutter, Benign Prostatic Hypertrophy, Bronchial Asthma, Erectile Dysfunction (ED), Gastroesophageal Reflux Disease (GERD), Gout, Hemorrhoids, Intervertebral Disc Degeneration, Ischemic Heart Disease, Menopausal and Postmenopausal Disorders, Migraine Headache, Osteoarthritis, Osteoporosis, Skin and Subcutaneous Infections, Urinary Incontinence, Vitamin D Deficiency
Languages:
English, Spanish
Description:
Dr. Patel graduated from the Baroda Medical College, Gujarat, India in 1992. He works in Dickinson, TX and specializes in Internal Medicine. Dr. Patel is affiliated with Clear Lake Regional Medical Center and Mainland Medical Center.
Vipulkumar Patel Photo 1

Vipulkumar G Patel

Specialties:
Internal Medicine
General Practice
Education:
Medical College Baroda (1992)

License Records

Vipulkumar Joitaram Patel

Address:
Macon, GA 31220
Licenses:
License #: 5501012515 - Expired
Category: Physical Therapy
Issued Date: Aug 18, 2005
Expiration Date: Jul 31, 2016
Type: Physical Therapist

Vipulkumar Patel resumes & CV records

Resumes

Vipulkumar Patel Photo 21

Vipulkumar Patel

Location:
United States
Vipulkumar Patel Photo 22

Graduate Student At Midwestern State University

Position:
Graduate Assistant at Midwestern State University
Location:
Wichita Falls, Texas
Industry:
Biotechnology
Work:
Midwestern State University - Wichita Falls, Texas Area since Aug 2010
Graduate Assistant
Education:
Hemchandracharya North Gujarat University 2004 - 2008
B. Pharm, pharmaceutical science Midwestern State University
MS, biology

Publications & IP owners

Us Patents

Method For Fabricating A Charge Coupled Device

US Patent:
6649454, Nov 18, 2003
Filed:
Nov 10, 2000
Appl. No.:
09/709927
Inventors:
Pradyumna Kumar Swain - Franklin Park NJ
Vipulkumar Kantilal Patel - South Brunswick NJ
Assignee:
Sarnoff Corporation - Princeton NJ
International Classification:
H01L 21339
US Classification:
438146, 438144, 438 60, 438 75
Abstract:
A process for forming a portion of a charge coupled device (CCD) is described. More particularly, wells ( ) are formed self-aligned under gate stacks ( ). By forming wells ( ) self-aligned to respective first and second gates ( ) of gate stacks ( ), potential for misalignment is reduced. First gates ( ) of gate stacks ( ) may be coupled together, and second gates ( ) of gate stacks ( ) may be coupled together, and these first and second gates ( ) may be coupled to respective signal sources ( ) to form a two-phase CCD.

Cmos-Compatible Integration Of Silicon-Based Optical Devices With Electronic Devices

US Patent:
6968110, Nov 22, 2005
Filed:
Apr 21, 2004
Appl. No.:
10/828898
Inventors:
Vipulkumar Patel - Monmouth Junction NJ, US
Margaret Ghiron - Allentown PA, US
Prakash Gothoskar - Allentown PA, US
Robert Keith Montgomery - Easton PA, US
Kalpendu Shastri - Orefield PA, US
Soham Pathak - Allentown PA, US
Katherine A. Yanushefski - Zionsville PA, US
Assignee:
SiOptical, Inc. - Allentown PA
International Classification:
G02B006/10
US Classification:
385131, 257431
Abstract:
A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.

Tapered Structure For Providing Coupling Between External Optical Device And Planar Optical Waveguide And Method Of Forming The Same

US Patent:
6993225, Jan 31, 2006
Filed:
Feb 10, 2004
Appl. No.:
10/775872
Inventors:
Vipulkumar Kantilal Patel - Monmouth Junction NJ, US
Prakash Gothoskar - Allentown PA, US
Robert Keith Montgomery - Easton PA, US
Margaret Ghiron - Allentown PA, US
Assignee:
SiOptical, Inc. - Allentown PA
International Classification:
G02B 6/26
H01L 21/02
US Classification:
385 43, 385 30, 438 31, 438 40
Abstract:
Methods of forming a tapered evanescent coupling region for use with a relatively thin silicon optical waveguide formed with, for example, an SOI structure. A tapered evanescent coupling region is formed in a silicon substrate that is used as a coupling substrate, the coupling substrate thereafter joined to the SOI structure. A gray-scale photolithography process is used to define a tapered region in photoresist, the tapered pattern thereafter transferred into the silicon substrate. A material exhibiting a lower refractive index than the silicon optical waveguide layer (e. g. , silicon dioxide) is then used to fill the tapered opening in the substrate. Advantageously, conventional silicon processing steps may be used to form coupling facets in the silicon substrate (i. e. , angled surfaces, V-grooves) in an appropriate relation to the tapered evanescent coupling region. The coupling facets may be formed contiguous with the tapered evanescent coupling region, or formed through the opposing side of the silicon substrate.

Low Loss Soi/Cmos Compatible Silicon Waveguide And Method Of Making The Same

US Patent:
7118682, Oct 10, 2006
Filed:
Mar 23, 2004
Appl. No.:
10/806738
Inventors:
Vipulkumar Kantilal Patel - Monmouth Junction NJ, US
Prakash Gothoskar - Allentown PA, US
Robert Keith Montgomery - Easton PA, US
Margaret Ghiron - Allentown PA, US
Assignee:
SiOptical, Inc. - Allentown PA
International Classification:
B29D 11/00
US Classification:
216 24, 216 46, 438 31, 438689
Abstract:
A method and structure for reducing optical signal loss in a silicon waveguide formed within a silicon-on-insulator (SOI) structure uses CMOS processing techniques to round the edges/corners of the silicon material along the extent of the waveguiding region. One exemplary set of processes utilizes an additional, sacrificial silicon layer that is subsequently etched to form silicon sidewall fillets along the optical waveguide, the fillets thus “rounding” the edges of the waveguide. Alternatively, the sacrificial silicon layer can be oxidized to consume a portion of the underlying silicon waveguide layer, also rounding the edges. Instead of using a sacrificial silicon layer, an oxidation-resistant layer may be patterned over a blanket silicon layer, the pattern defined to protect the optical waveguiding region. A thermal oxidation process is then used to convert the exposed portion of the silicon layer into silicon dioxide, forming a bird's beak structure at the edges of the silicon layer, thus defining the “rounded” edges of the silicon waveguiding structure.

Silicon-Based Schottky Barrier Infrared Optical Detector

US Patent:
7358585, Apr 15, 2008
Filed:
Nov 17, 2004
Appl. No.:
10/990725
Inventors:
Vipulkumar Patel - Monmouth Junction NJ, US
Margaret Ghiron - Allentown PA, US
Prakash Gothoskar - Allentown PA, US
Robert Keith Montgomery - Easton PA, US
Soham Pathak - Allentown PA, US
David Piede - Allentown PA, US
Kalpendu Shastri - Orefield PA, US
Katherine A. Yanushefski - Zionsville PA, US
Assignee:
SiOptical, Inc. - Allentown PA
International Classification:
G02B 6/10
H01L 31/0224
US Classification:
257454, 257E29143, 385129
Abstract:
A silicon-based IR photodetector is formed within a silicon-on-insulator (SOI) structure by placing a metallic strip (preferably, a silicide) over a portion of an optical waveguide formed within a planar silicon surface layer (i. e. , “planar SOI layer”) of the SOI structure, the planar SOI layer comprising a thickness of less than one micron. Room temperature operation of the photodetector is accomplished as a result of the relatively low dark current associated with the SOI-based structure and the ability to use a relatively small surface area silicide strip to collect the photocurrent. The planar SOI layer may be doped, and the geometry of the silicide strip may be modified, as desired, to achieve improved results over prior art silicon-based photodetectors.

Low Loss Soi/Cmos Compatible Silicon Waveguide

US Patent:
7499620, Mar 3, 2009
Filed:
Sep 6, 2006
Appl. No.:
11/516217
Inventors:
Vipulkumar Kantilal Patel - Monmouth Junction NJ, US
Prakash Gothoskar - Allentown PA, US
Robert Keith Montgomery - Easton PA, US
Margaret Ghiron - Allentown PA, US
Assignee:
Lightwire, Inc. - Allentown PA
International Classification:
G02B 6/10
US Classification:
385130
Abstract:
A method and structure for reducing optical signal loss in a silicon waveguide formed within a silicon-on-insulator (SOI) structure uses CMOS processing techniques to round the edges/corners of the silicon material along the extent of the waveguiding region. One exemplary set of processes utilizes an additional, sacrificial silicon layer that is subsequently etched to form silicon sidewall fillets along the optical waveguide, the fillets thus “rounding” the edges of the waveguide. Alternatively, the sacrificial silicon layer can be oxidized to consume a portion of the underlying silicon waveguide layer, also rounding the edges. Instead of using a sacrificial silicon layer, an oxidation-resistant layer may be patterned over a blanket silicon layer, the pattern defined to protect the optical waveguiding region. A thermal oxidation process is then used to convert the exposed portion of the silicon layer into silicon dioxide, forming a bird's beak structure at the edges of the silicon layer, thus defining the “rounded” edges of the silicon waveguiding structure.

Cmos-Compatible Integration Of Silicon-Based Optical Devices With Electronic Devices

US Patent:
2005023, Oct 27, 2005
Filed:
Jun 29, 2005
Appl. No.:
11/169932
Inventors:
Vipulkumar Patel - Monmouth Junction NJ, US
Margaret Ghiron - Allentown PA, US
Prakash Gothoskar - Allentown PA, US
Robert Montgomery - Easton PA, US
Kalpendu Shastri - Orefield PA, US
Soham Pathak - Allentown PA, US
Katherine Yanushefski - Zionsville PA, US
International Classification:
H01L029/04
US Classification:
257057000
Abstract:
A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.

Patterning Silicon Carbide Films

US Patent:
5958793, Sep 28, 1999
Filed:
Dec 24, 1997
Appl. No.:
8/998353
Inventors:
Vipulkumar K. Patel - South Brunswick NJ
Lawrence K. White - Princeton Jct. NJ
Lawrence A. Goodman - Plainsboro NJ
Assignee:
Sarnoff Corporation - Princeton NJ
International Classification:
H01L 213065
H01L 21314
H01L 21316
H01L 21318
US Classification:
438689
Abstract:
A method of etching an opening having tapered wall in a layer of silicon carbide (SiC) includes forming a layer of a resist on the SiC layer. An opening having tapered wall is formed in the resist layer so as to expose a portion of the SiC layer. The exposed portion of the SiC layer is then exposed to a plasma of a gas containing carbon and fluorine to etch an opening through the SiC layer with the opening having tapered walls. If a layer of a glass is provided under the SiC layer, the plasma will also etch through the glass layer to provide an opening in the glass layer having tapered walls.

Possible Relatives

David Patel  Dawood M Patel  Daxa R Patel  Daxaben C Patel  Daxesh T Patel  Daxeshkumar B Patel  Dayalji D Patel  Vipulkumar A Rana 

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