Vivian P Chou, 445987 Prospect Rd, San Jose, CA 95129

6804772, Oct 12, 2004

Mar 21, 2001

09/815098

Sherman Lee - Rancho Palos Verdes CA
Vivian Y. Chou - Alhambra CA
John H. Lin - Downey CA

Broadcom Corporation - Irvine CA

G06F 1202

712248, 711149, 711152

A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

7167727, Jan 23, 2007

Sep 30, 2003

10/674693

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Y. Chou - Alhambra CA, US
John H. Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 1/38

455557, 455 412, 455259, 455265

A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e. g. , including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver. A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system.

7228392, Jun 5, 2007

Apr 15, 2003

10/413689

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Y. Chou - Alhambra CA, US
John H. Lin - Downey CA, US

Broadcom Corporation - Irvine CA

G06F 12/02

711154

A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

7277420, Oct 2, 2007

Nov 13, 2002

10/293452

Vivian Chou - Alhambra CA, US
Charles Aragones - Los Angeles CA, US
Sherman Lee - Rancho Palos Verdes CA, US

Broadcom Corporation - Irvine CA

H04J 3/06

370350, 455 412, 4555501, 4555531, 370338, 375242

A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder operably couples to the input buffer and receives the packetized audio data from the input buffer. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC). The processor operably couples to the WLAN interface, the input buffer, and the transcoder. The transcoder outputs the PCM audio data to the audio CODEC such that the PCM audio data is substantially temporally aligned with Radio Frequency (RF) slots of the WLAN interface.

7389094, Jun 17, 2008

Apr 30, 2007

11/796837

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Y. Chou - Alhambra CA, US
John H. Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 1/06

455259, 455 411, 455265, 375372

A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

7403141, Jul 22, 2008

Nov 8, 2002

10/291006

Charles Aragones - Los Angeles CA, US
Sherman Lee - Rancho Palos Verdes CA, US
Vivian Chou - Alhambra CA, US

Broadcom Corporation - Irvine CA

H03M 1/00

341126, 4555501

A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one WLAN device to receive inbound packetized audio data from the at least one WLAN device and to transmit outbound packetized audio data to the at least one WLAN device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

7411934, Aug 12, 2008

Nov 13, 2002

10/293111

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Chou - Alhambra CA, US
Charles Aragones - Los Angeles CA, US
John Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04Q 7/24

370338, 370419, 455 412

A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface.

7640418, Dec 29, 2009

Aug 9, 2004

10/914105

Sherman Lee - Rancho Palos Verdes CA, US
Vivian Y. Chou - Alhambra CA, US
John H. Lin - Downey CA, US

Broadcom Corporation - Irvine CA

G06F 9/30

712205, 711170, 712214, 712248

A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.