Wayne T Yamamoto Deceased982 Glenridge Dr, San Jose, CA 95136

6725338, Apr 20, 2004

Nov 19, 2001

09/992085

Christopher A. Gomez - Cupertino CA
Wayne I. Yamamoto - Saratoga CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1200

711137, 711138, 711140, 711154, 712235

A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, determining whether a miss occurs for the speculative load, and preventing use of the marked speculative load by the microprocessor if a miss occurs. A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, inserting the marked speculative load into a load miss queue, determining whether a miss occurs for the speculative load, and preventing the load miss queue from committing the marked speculative load to cache if a miss occurs.

6934830, Aug 23, 2005

Sep 26, 2002

10/259721

Sudarshan Kadambi - Hayward CA, US
Adam R. Talcott - San Jose CA, US
Wayne I. Yamamoto - Saratoga CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F009/30

712214, 711125, 712219

One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

6948032, Sep 20, 2005

Jan 29, 2003

10/354327

Sudarshan Kadambi - Hayward CA, US
Vijay Balakrishnan - Mountain View CA, US
Wayne I. Yamamoto - Saratoga CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F012/00

711120, 711133, 711141

One embodiment of the present invention provides a system that uses a hot spot cache to alleviate the performance problems caused by hot spots in cache memories, wherein the hot spot cache stores lines that are evicted from hot spots in the cache. Upon receiving a memory operation at the cache, the system performs a lookup for the memory operation in both the cache and the hot spot cache in parallel. If the memory operation is a read operation that causes a miss in the cache and a hit in the hot spot cache, the system reads a data line for the read operation from the hot spot cache, writes the data line to the cache, performs the read operation on the data line in the cache, and then evicts the data line from the hot spot cache.

6976125, Dec 13, 2005

Jan 29, 2003

10/354329

Sudarshan Kadambi - Hayward CA, US
Vijay Balakrishnan - Mountain View CA, US
Wayne I. Yamamoto - Saratoga CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F012/02

711120, 711133, 711137

One embodiment of the present invention provides a system for predicting hot spots in a cache memory. Upon receiving a memory operation at the cache, the system determines a target location within the cache for the memory operation. Once the target location is determined, the system increments a counter associated with the target location. If the counter reaches a pre-determined threshold value, the system generates a signal indicating that the target location is a hot spot in the cache memory.

2002006, May 23, 2002

Nov 19, 2001

09/993074

Christopher Gomez - Campbell CA, US
Wayne Yamamoto - Saratoga CA, US

G06T011/20
G06F009/44
G06F013/10

703/021000, 345/440000

A method and apparatus of visualizing events within a microprocessor include simulating the operation of a microprocessor for a set of instructions, generating the internal state information from the simulation and graphically displaying an execution behavior based on the internal state information. The graphical display represents a flow of the instructions through an internal pipeline in the microprocessor. Execution behavior is selectively displayed based on type of behavior and clock cycle the execution occurred during on the microprocessor. A log of the execution behavior of the set of instructions on the microprocessor is created. The set of instructions is created from a graphical display of selectable instructions.

2013003, Jan 31, 2013

Jul 26, 2011

13/191438

Brian Kelleher - Palo Alto CA, US
Emmett M. Kilgariff - San Jose CA, US
Wayne Yamamoto - Saratoga CA, US

NVIDIA CORPORATION - Santa Clara CA

G06F 12/08

711203, 711E12016

Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

5692146, Nov 25, 1997

May 26, 1995

8/451742

Wayne Yamamoto - San Jose CA
Narendra Sankar - Sunnyvale CA
Mario Nemirovsky - San Jose CA

National Semiconductor Corporation - Santa Clara CA

G06F 926
G06F 932
G06F 1200
G06F 1202

395410

An efficient method for implementing string operations used to process blocks of data within a memory. The registers used to track the memory addresses are updated and committed before the outcome of a read or write address operation is known. In the event an exception occurs, exception handling hardware and microcode is used to restore the state of the registers to the condition they were in prior to the iteration which produced the exception. This reduces the number of microcode instructions required to implement the string operation, producing a faster cycling of the code through multiple iterations. The result is a more optimal code for string operations and a decrease in the time required to carry out the string instruction.

5710887, Jan 20, 1998

Aug 29, 1995

8/520627

Raman Chelliah - San Carlos CA
Jason S. Cornez - Belmont CA
Carl Dellar - Cupertino CA
Stephen Harrison - Cambridge MA
John A. Hempe - Foster City CA
Chih-Cheng Hsu - Fremont CA
Eric J. Golin - Menlo Park CA
Charles A. Price - San Jose CA
Neal S. Rutta - Willow Glen CA
Thomas A. Wood - Mountain View CA
Wayne K. Yamamoto - San Francisco CA

Broadvision - Los Altos CA

G06F 1562

395226

A system for facilitating commercial transactions, between a plurality of customers and at least one supplier of items over a computer driven network capable of providing communications between the supplier and at least one customer site associated with each customer. Each site includes an associated display and an input device through which the customer can input information into the system. At least one supplier is presented on the display for selection by the customer using the input device. Similarly items from a supplier can be displayed for the customer to observe. Associated with a supplier of such items is an item database including information on presented items. Pricing subsystem receives information from the item database to determine the cost associated with a presented item. In addition a customer information database stores information relating to the customer. Associated with each customer is a customer monitoring object for each customer.