Wilson C Chen, 62Fontana, CA

8536913, Sep 17, 2013

Feb 8, 2012

13/368956

Wilson J. Chen - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03L 7/06

327157, 375374

Output driver feedback circuitry limits output slew rates across a wide range of output loads. A transition time lock loop architecture of the feedback circuitry compares a transition time pulse with a reference pulse to adjusts transition time of an output signal for various process-voltage-temperature (PVT) process corners, output voltage domains and output capacitances. Reference pulse generation circuitry provides a reference pulse in phase with the transition time pulse for each rise and fall of the output signal.

8633738, Jan 21, 2014

Feb 8, 2012

13/368870

Wilson J. Chen - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03B 1/00

327111, 327112, 327170

Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

8638131, Jan 28, 2014

Feb 23, 2011

13/032808

Wilson J. Chen - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03K 3/00

327108, 327170

In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.

2013018, Jul 18, 2013

Feb 8, 2012

13/368906

Wilson J. Chen - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03K 5/06

327277

Process, voltage and temperature corners of an on-chip device under calibration are obtained by comparing the outputs of different on-chip components such as active on-chip components and passive-on chip components in response to an input. A first on-chip delay line including a number of active devices, which generate an array of outputs D[ ]) at different stages of the delay. A second on-chip delay line generates a single output (CLK). A DFF array samples the array of outputs (D[ ]) with the single output clock CLK. The different delay variations in different process and temperature corners cause different outputs from the DFF array. The different outputs from the DFF array provide information about the process and temperature corner that can be for rapid calibration of the on-chip device under calibration within one cycle of the CLK.

2021011, Apr 15, 2021

Aug 31, 2020

17/008068

- San Diego CA, US
Wilson Jianbo CHEN - San Diego CA, US

H03K 19/0185
H03K 19/0175
H03K 19/003

An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

2019028, Sep 19, 2019

Jan 30, 2019

16/262267

- San Diego CA, US
Richard Dominic WIETFELDT - San Diego CA, US
Helena Deirdre O'SHEA - San Diego CA, US
Wolfgang ROETHIG - San Jose CA, US
Christopher Kong Yee CHUN - Austin TX, US
ZhenQi CHEN - South Boston MA, US
Scott DAVENPORT - Merrimack NH, US
Wilson CHEN - San Diego CA, US
Umesh SRIKANTIAH - San Diego CA, US

G06F 13/24
G06F 13/42

Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

2018028, Oct 4, 2018

Apr 3, 2017

15/478063

- San Diego CA, US
Wilson Chen - San Diego CA, US

H03K 19/00
H03K 17/687
H03K 19/0185

The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

2018028, Oct 4, 2018

Mar 13, 2018

15/920270

- San Diego CA, US
Helena Deirdre O'SHEA - San Diego CA, US
ZhenQi CHEN - Shirley MA, US
Wilson Jianbo CHEN - San Diego CA, US
Richard Dominic WIETFELDT - San Diego CA, US

H04L 27/00
H03K 3/011
H03K 5/01
H04B 3/46
H04B 3/06
H04L 25/02
H04L 25/03
H04L 29/06

Systems, methods, and apparatus for managing digital communication interfaces coupled to data communication links are disclosed. In one example, the digital communication interfaces provide methods, protocols and techniques that may be used to provide a common slew rate for signals transmitted on a communication link that may be operated at multiple different voltage ranges. A method may include determining a first voltage range defined for transmitting signals over the communication link when the over the communication link is operated in a first mode of operation, configuring a line driver to operate within the first voltage range with a common slew rate that applies to each of a plurality of modes of operation, and transmitting first data over the communication link in one or more signals that switch within the first voltage range with the common slew rate. Each mode of operation may define a different voltage range for transmitting signals.