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Zhen G Chen, 65726 Athens St, San Francisco, CA 94112

Zhen Chen Phones & Addresses

726 Athens St, San Francisco, CA 94112    415-6407505   

Pittsburg, CA   

Antioch, CA   

Boston, MA   

Lakewood, WA   

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Zhen Chen Photo 1

Zhen Chen - Lawyer

Address:
Fangda Partners
105-7695634 (Office)
Licenses:
New York - Currently registered 2008
Education:
Northwestern University School of Law

Publications & IP owners

Wikipedia

Zhen Chen Photo 38

Chen Zhen (Fictial Character) The Free ...

Chen Zhen is a fictional Chinese martial artist and hero created by Hong Kong writer Ni Kuang. He made his debut appearance in the 1972 film Fist of Fury, which ...
Zhen Chen Photo 39

Chen Zhen

Chen Zhen may refer to: Chen Zhen (Han Dynasty), Han Dynasty minister serving under Liu Bei Chen Zhen (fictional character), fictional Chinese martial artist who was ...

Us Patents

Laterally Contacted Blue Led With Superlattice Current Spreading Layer

US Patent:
8395165, Mar 12, 2013
Filed:
Jul 8, 2011
Appl. No.:
13/178497
Inventors:
Zhen Chen - Pleasanton CA, US
William Fenwick - Livermore CA, US
Steve Lester - Palo Alto CA, US
Assignee:
Bridelux, Inc. - Livermore CA
International Classification:
H01L 27/15
US Classification:
257 79, 257 78, 257E33008, 257E33034, 257E33049, 438 22
Abstract:
A laterally contacted blue LED device involves a PAN structure disposed over an insulating substrate. The substrate may be a sapphire substrate that has a template layer of GaN grown on it. The PAN structure includes an n-type GaN layer, a light-emitting active layer involving indium, and a p-type GaN layer. The n-type GaN layer has a thickness of at least 500 nm. A Low Resistance Layer (LRL) is disposed between the substrate and the PAN structure such that the LRL is in contact with the bottom of the n-layer. In one example, the LRL is an AlGaN/GaN superlattice structure whose sheet resistance is lower than the sheet resistance of the n-type GnA layer. The LRL reduces current crowding by conducting current laterally under the n-type GaN layer. The LRL reduces defect density by preventing dislocation threads in the underlying GaN template from extending up into the PAN structure.

Led On Silicon Substrate Using Zinc-Sulfide As Buffer Layer

US Patent:
2013003, Feb 7, 2013
Filed:
Aug 3, 2011
Appl. No.:
13/197765
Inventors:
Zhen Chen - Pleasanton CA, US
Assignee:
Bridgelux, Inc. - Livermore CA
International Classification:
H01L 33/32
H01L 33/02
US Classification:
257 76, 438 33, 257E33025, 257E33048, 257 94
Abstract:
A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices.

Led Having A Low Defect N-Type Layer That Has Grown On A Silicon Substrate

US Patent:
2013003, Feb 7, 2013
Filed:
Aug 2, 2011
Appl. No.:
13/196854
Inventors:
Zhen Chen - Pleasanton CA, US
Assignee:
Bridgelux, Inc. - Livermore CA
International Classification:
H01L 33/32
H01L 33/22
H01L 33/06
H01L 33/04
US Classification:
257 94, 438 47, 438 33, 438 29, 438 46, 257E33049, 257E3301, 257E33043
Abstract:
A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device.

N-Type Gallium-Nitride Layer Having Multiple Conductive Intervening Layers

US Patent:
2013003, Feb 7, 2013
Filed:
Aug 2, 2011
Appl. No.:
13/196828
Inventors:
Zhen Chen - Pleasanton CA, US
Yi Fu - Hacienda Heights CA, US
Assignee:
Bridgelux, Inc. - Livermore CA
International Classification:
H01L 33/32
H01L 33/58
US Classification:
257 95, 438 29, 257 94, 257E33074, 257E33025
Abstract:
A vertical GaN-based blue LED has an n-type layer comprising multiple conductive intervening layers. The n-type layer contains a plurality of periods. Each period of the n-type layer includes a gallium-nitride (GaN) sublayer and a thin conductive aluminum-gallium-nitride (AlGaN:Si) intervening sublayer. In one example, each GaN sublayer has a thickness substantially more than 100 nm and less than 1000 nm, and each AlGaN:Si intervening sublayer has a thickness less than 25 nm. The entire n-type layer is at least 2000 nm thick. The AlGaN:Si intervening layer provides compressive strain to the GaN sublayer thereby preventing cracking. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form a finished LED device. Because the AlGaN:Si sublayers are conductive, the entire n-type layer can remain as part of the finished LED device.

Buffer Layer For Gan-On-Si Led

US Patent:
2013005, Mar 7, 2013
Filed:
Sep 7, 2011
Appl. No.:
13/227406
Inventors:
Zhen Chen - Pleasanton CA, US
Assignee:
Bridgelux, Inc. - Livermore
International Classification:
H01L 33/32
H01L 33/48
US Classification:
257 76, 438 47, 438 33, 257E33025, 257E33056
Abstract:
A buffer layer of zinc telluride (ZnTe) or titanium dioxide (TiO) is formed directly on a silicon substrate. Optionally, a layer of AlN is then formed as a second layer of the buffer layer. A template layer of GaN is then formed over the buffer layer. An epitaxial LED structure for a GaN-based blue LED is formed over the template layer, thereby forming a first multilayer structure. A conductive carrier is then bonded to the first multilayer structure. The silicon substrate and the buffer layer are then removed, thereby forming a second multilayer structure. Electrodes are formed on the second multilayer structure, and the structure is singulated to form blue LED devices.

Optoelectronic Device Based On Non-Polar And Semi-Polar Aluminum Indium Nitride And Aluminum Indium Gallium Nitride Alloys

US Patent:
2013012, May 23, 2013
Filed:
Dec 18, 2012
Appl. No.:
13/718152
Inventors:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA, US
Zhen Chen - Goleta CA, US
James S. Speck - Goleta CA, US
Steven P. DenBaars - Goleta CA, US
Shuji Nakamura - Santa Barbara CA, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA
International Classification:
H01L 33/30
US Classification:
257 13
Abstract:
A high-power and high-efficiency light emitting device with emission wavelength (λ) ranging from 280 nm to 360 nm is fabricated. The new device structure uses non-polar or semi-polar AlInN and AlInGaN alloys grown on a non-polar or semi-polar bulk GaN substrate.

Semiconductor Device Containing Stress Relaxation Layer And Method Of Making Thereof

US Patent:
2021034, Nov 4, 2021
Filed:
Apr 26, 2021
Appl. No.:
17/240342
Inventors:
- Lund, SE
Zhen CHEN - Dublin CA, US
International Classification:
H01L 33/12
H01L 33/00
H01L 33/06
H01L 33/08
H01L 33/24
H01L 33/32
H01L 33/40
H01L 33/44
Abstract:
A structure includes a first material layer, a second material layer, and a stress relaxation layer having a thickness of 0.5 nm or less between the first material layer and the second material layer.

Light Emitting Diode Containing Pinhole Masking Layer And Method Of Making Thereof

US Patent:
2021025, Aug 19, 2021
Filed:
Feb 16, 2021
Appl. No.:
17/176857
Inventors:
- Lund, SE
Zhen CHEN - Dublin CA, US
International Classification:
H01L 33/00
H01L 21/02
H01L 33/12
Abstract:
A structure includes a first material layer, a second material layer, and a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the second material of second material layer located between the first material layer and the second material layer. A method of forming a LED includes forming a buffer layer over a support substrate, forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the semiconductor buffer layer, forming a n-doped semiconductor material layer on the dielectric masking layer such that the n-doped semiconductor material of the n-doped semiconductor layer fills the pinholes and contacts the buffer layer, forming an active region over the n-doped semiconductor material layer, and forming a p-doped semiconductor material layer over the active region.

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