Zheng Yanping G Luo, 5210508 Pointeview Dr, Austin, TX 78738

6385704, May 7, 2002

Nov 14, 1997

08/969884

Raghunath Rao - Austin TX
Miroslav Dokic - Austin TX
Zheng Luo - Austin TX
Jeffrey Niehaus - Austin TX
James Divine - Austin TX

Cirrus Logic, Inc.

G06F 1200

711151, 711152

A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.

2003009, May 15, 2003

Mar 30, 2001

09/821897

Zheng Luo - Austin TX, US
Gregory North - Austin TX, US

G06F001/26
G06F001/32

713/320000

A system-on-a-chip includes a first and second power planes for respectively powering core logic and analog portions of the system. Clock generation circuitry is included for generating clocks for clocking operations of selected circuits of the system on a chip in response to a signal generated by an oscillator. Power control circuitry switches off power to the first and second power planes in a first mode, with the oscillator being enabled. In a second mode, the power control circuitry disables the clock generation circuitry and switches power to the first and second power planes, the oscillator being enabled.

2005009, May 5, 2005

Aug 6, 2004

10/913574

John Yuan - Austin TX, US
Steven Smith - Austin TX, US
Srikrishna Ramaswamy - Austin TX, US
Zheng Luo - Austin TX, US

VisionFlow, Inc. - Austin TX

H04N007/12

375240160, 375240030, 375240180, 375240120

A system, method, and computer readable medium adapted to provide software and hardware partitioning for multi-standard video compression and decompression comprises a master-slave bus, a peer-to-peer bus, and an inter-processor communications bus, a prediction engine, a filter engine, and a transform engine, and a video encode control processor, and a video decode control processor adapted to utilize the master-slave bus to interact with the video hardware engines for control flow processing, the peer-to-peer bus for data flow processing, and the inter-processor communications bus for inter-processor communications, and a system data bus adapted to permit data exchange between system resources, the busses, the engines, and the processors.

6101598, Aug 8, 2000

Nov 14, 1997

8/970372

Miroslav Dokic - Austin TX
Raghunath Rao - Austin TX
Zheng Luo - Austin TX
Jeffrey Niehaus - Austin TX
James Divine - Austin TX

Cirrus Logic, Inc.

G06F 0944

712227

A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

6081783, Jun 27, 2000

Nov 14, 1997

8/970979

James Divine - Austin TX
Jeffrey Niehaus - Austin TX
Miroslav Dokic - Austin TX
Raghunath Rao - Austin TX
Terry Ritchie - Austin TX
Baker Scott - Boulder CO
John Pacourek - Austin TX
Zheng Luo - Austin TX

Cirrus Logic, Inc.

G10L 2100

704500

An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

6145007, Nov 7, 2000

Nov 14, 1997

8/969883

Miroslav Dokic - Austin TX
Raghunath Rao - Austin TX
Jeffrey Niehaus - Austin TX
Zheng Luo - Austin TX
James Divine - Austin TX

Cirrus Logic, Inc.

G06F 1300

709230

A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

6316991, Nov 13, 2001

Mar 29, 2000

9/537605

Gabriel Patrick Muyshondt - Austin TX
Zheng Luo - Austin TX

Cirrus Logic, Inc.

G05F 110
G05F 302

327543

A voltage out-of-calibration detector 200 includes a voltage divider operating between first and second voltage rails and having a plurality of taps 203 for generating first and second comparison voltages. A first set of switches 205 selectively couples at least one of the plurality of taps 203 to the input of a first voltage comparator 401a, first voltage comparator 401a comparing the first comparison voltage with an input voltage and outputing a signal when the input voltage exceeds the first comparison voltage. A second set of switches 206 selectively couples at least one of the plurality of taps 203 to an input of a second voltage comparator 401b, second voltage comparator 401b comparing the second comparison voltage with the input voltage and outputing a signal when the input voltage is below the second comparison voltage. Control logic 300 selectively activates the first and second sets of switches 205/206 in response to received control signals.

6253293, Jun 26, 2001

Jan 14, 2000

9/483290

Raghunath Rao - Austin TX
Miroslav Dokic - Austin TX
Zheng Luo - Austin TX
Jeffrey Niehaus - Austin TX
James Divine - Austin TX

Cirrus Logic, Inc.

G06F 1200
G06F 1700
G06F 15167
G10L 2100

711147

A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.