Girish B Desai, 5340720 Las Palmas Ave, Fremont, CA 94539
Girish Desai Phones & Addresses
Fremont, CA
10860 Northoak Sq, Cupertino, CA 95014
175 Calvert Dr, Cupertino, CA 95014 408-3667486
Santa Clara, CA
Milpitas, CA
Garland, TX
Chino, CA
Sunnyvale, CA
San Jose, CA
Mentions for Girish B Desai
Publications & IP owners
Us Patents
Usb Device Communication Apparatus, Systems, And Methods
US Patent:
7853725, Dec 14, 2010
Filed:
Jun 19, 2007
Appl. No.:
11/765287
Inventors:
Girish Desai - Santa Clara CA, US
Senthil Chellamuthu - Mountain View CA, US
Senthil Chellamuthu - Mountain View CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 3/00
G06F 5/00
G06F 5/00
US Classification:
710 5, 710 36
Abstract:
Methods, systems and apparatus may operate to send and receive universal serial bus (USB) control endpoint standard device requests with embedded functional sub-requests. From the USB device perspective, such operations may comprise receiving a control endpoint standard device request from a host at the USB device, decoding the functional sub-request forming a first portion of the control endpoint standard device request, decoding data forming a second portion of the control endpoint standard device request, and executing the functional sub-request by the USB device. Other methods, systems, and apparatus are disclosed.
Usb Device Communication Apparatus, Systems, And Methods
US Patent:
8335865, Dec 18, 2012
Filed:
Nov 30, 2010
Appl. No.:
12/957081
Inventors:
Girish Desai - Santa Clara CA, US
Senthil Chellamuthu - Mountain View CA, US
Senthil Chellamuthu - Mountain View CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 3/00
G06F 5/00
G06F 5/00
US Classification:
710 5, 710 36
Abstract:
Some embodiments include methods and apparatus to decode a functional request embedded in a portion of a standard device request, and execute the functional request by a universal serial bus (USB) device. The standard device request can include a Get_Descriptor request. Other embodiments are described.
Usb Device Communication Apparatus, Systems, And Methods
US Patent:
8402173, Mar 19, 2013
Filed:
Sep 14, 2012
Appl. No.:
13/616858
Inventors:
Girish Desai - Santa Clara CA, US
Senthil Chellamuthu - Mountain View CA, US
Senthil Chellamuthu - Mountain View CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 3/00
G06F 5/00
G06F 5/00
US Classification:
710 5, 710 36
Abstract:
Some embodiments include methods and apparatus to decode a functional request embedded in a portion of a standard device request, and execute the functional request by a universal serial bus (USB) device. The standard device request can include a Get_Descriptor request. Other embodiments are described.
Ssd Architecture Supporting Low Latency Operation
US Patent:
2022021, Jul 7, 2022
Filed:
Mar 21, 2022
Appl. No.:
17/700321
Inventors:
- Tokyo, JP
Mark Carlson - Longmont CO, US
Amit Jain - Cupertino CA, US
Narasimhulu Dharani Kotte - Fremont CA, US
Senthil Thangaraj - Fremont CA, US
Barada Mishra - Sunnyvale CA, US
Girish Desai - Cupertino CA, US
Mark Carlson - Longmont CO, US
Amit Jain - Cupertino CA, US
Narasimhulu Dharani Kotte - Fremont CA, US
Senthil Thangaraj - Fremont CA, US
Barada Mishra - Sunnyvale CA, US
Girish Desai - Cupertino CA, US
International Classification:
G06F 3/06
Abstract:
In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the first region in the first operation mode.
Ssd Architecture Supporting Low Latency Operation
US Patent:
2019004, Feb 7, 2019
Filed:
Nov 1, 2017
Appl. No.:
15/800742
Inventors:
- Tokyo, JP
Mark Carlson - Longmont CO, US
Amit Jain - Cupertino CA, US
Narasimhulu Dharani Kotte - Fremont CA, US
Senthil Thangaraj - Fremont CA, US
Barada Mishra - Sunnyvale CA, US
Girish Desai - Cupertino CA, US
Mark Carlson - Longmont CO, US
Amit Jain - Cupertino CA, US
Narasimhulu Dharani Kotte - Fremont CA, US
Senthil Thangaraj - Fremont CA, US
Barada Mishra - Sunnyvale CA, US
Girish Desai - Cupertino CA, US
International Classification:
G06F 3/06
Abstract:
In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the first region in the first operation mode.
Methods, Systems, And Computer Readable Media For Providing Flexible Host Memory Buffer
US Patent:
2016002, Jan 28, 2016
Filed:
Jul 30, 2015
Appl. No.:
14/814460
Inventors:
- Plano TX, US
Eran Erez - Bothell WA, US
Sebastien Andre Jean - Boise ID, US
Girish Bhaurao Desai - Cupertino CA, US
Venkata Krishna Nadh Dhulipala - San Jose CA, US
Eran Erez - Bothell WA, US
Sebastien Andre Jean - Boise ID, US
Girish Bhaurao Desai - Cupertino CA, US
Venkata Krishna Nadh Dhulipala - San Jose CA, US
International Classification:
G06F 3/06
G06F 12/08
G06F 12/02
G06F 12/08
G06F 12/02
Abstract:
Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.
Datapath Management In A Memory Controller
US Patent:
2015023, Aug 20, 2015
Filed:
Feb 19, 2014
Appl. No.:
14/184208
Inventors:
- Plano TX, US
Abhijeet Manohar - Karnataka, IN
Venkata Krishna Nadh Dhulipala - San Jose CA, US
Girish B. Desai - Cupertino CA, US
Abhijeet Manohar - Karnataka, IN
Venkata Krishna Nadh Dhulipala - San Jose CA, US
Girish B. Desai - Cupertino CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G06F 13/18
G06F 13/28
G06F 13/28
Abstract:
A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.
Buffer Memory Reservation Techniques For Use With A Nand Flash Memory
US Patent:
2015001, Jan 15, 2015
Filed:
Jul 11, 2013
Appl. No.:
13/940050
Inventors:
- Plano TX, US
Robert Jackson - Milpitas CA, US
Yoav Weinberg - Thornhill, CA
William L. Guthrie - Santa Cruz CA, US
Girish B. Desai - Cupertino CA, US
Robert Jackson - Milpitas CA, US
Yoav Weinberg - Thornhill, CA
William L. Guthrie - Santa Cruz CA, US
Girish B. Desai - Cupertino CA, US
International Classification:
G06F 5/14
G06F 12/02
G06F 12/02
US Classification:
710 53
Abstract:
This disclosure provides examples of circuits, devices, systems, and methods for managing a buffer memory. Regions of the buffer memory are dynamically reserved, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.
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