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Venkata R KollaSan Mateo, CA

Venkata Kolla Phones & Addresses

San Mateo, CA   

Cupertino, CA   

Work

Company: Infosys - Pune, Maharashtra Aug 2008 Position: Software developer

Education

School / High School: University of Louisiana at Lafayette- Lafayette, LA Dec 2012 Specialities: Masters of Science in Computer Science

Mentions for Venkata R Kolla

Venkata Kolla resumes & CV records

Resumes

Venkata Kolla Photo 11

Venkata Kolla

Venkata Kolla Photo 12

Venkata Kolla

Position:
Consultant at Apollo Group
Location:
San Francisco Bay Area
Industry:
Wireless
Work:
Apollo Group since Feb 2010
Consultant
Education:
Chalmers University of Technology 2002 - 2004
University of Madras
Venkata Kolla Photo 13

Venkata Kolla - Hillsboro, OR

Work:
Infosys - Pune, Maharashtra Aug 2008 to Dec 2010
Software Developer
Advanced Micro Devices(AMD) - Sunnyvale, CA
Intern
Education:
University of Louisiana at Lafayette - Lafayette, LA Dec 2012
Masters of Science in Computer Science
Acharya Nagarjuna University - Guntur, Andhra Pradesh May 2008
Bachelors of Science

Publications & IP owners

Us Patents

Controlling Access To Memory Cells

US Patent:
2020009, Mar 26, 2020
Filed:
Sep 24, 2018
Appl. No.:
16/139162
Inventors:
- San Francisco CA, US
Joshua James Luft-Glidden - San Francisco CA, US
Radhika Nair - San Francisco CA, US
Fabrice Talbot - San Francisco CA, US
Srinivasa Gopaladasu - San Francisco CA, US
Venkata Kolla - San Francisco CA, US
Lucas Pfister - Millbrae CA, US
Chintan Tank - Dublin CA, US
Chaitanya Bhatt - San Francisco CA, US
International Classification:
G06F 3/06
Abstract:
A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.

Generating, Assigning, And Evaluating Different Versions Of A Test

US Patent:
2014033, Nov 13, 2014
Filed:
Oct 23, 2013
Appl. No.:
14/061747
Inventors:
- Phoenix AZ, US
VENKATA KOLLA - Union City CA, US
PAVAN ARIPIRALA VENKATA - Fremont CA, US
SUMIT KEJRIWAL - KARNATAKA, IN
NARENDER VATTIKONDA - San Jose CA, US
Assignee:
Apollo Group, Inc. - Phoenix AZ
International Classification:
G09B 7/00
US Classification:
434350
Abstract:
Method(s), stored instruction(s), and computing device(s) are provided for automatically generating different subsets of questions and/or automatically assigning the different subsets of questions to different test participants. The computing device(s) store information that includes test questions, test version generation criteria, and test version assignment criteria. The computing device(s) automatically determine, using the test version generation criteria, subsets of test questions that differ from each other by at least one question. The computing device(s) automatically assign, using the test version assignment criteria, subsets of test questions, which differ from each other by at least one question, to different test participants. The computing device(s) then cause administration of at least one of the different versions to at least one of the different test participants.

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